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There is an increasing demand in high-throughput mobile applications for programmability and energy efficiency. Conventional mobile Central Processing Units (CPUs) and Very Long Instruction Word (VLIW) processors cannot meet these demands. In this paper, we present a novel dynamically reconfigurable processor that targets these requirements. The processor consists of a heterogeneous array of coarse...
The main design requirements for high-throughput mobile applications are energy efficiency and programmability. This paper presents a novel dynamically reconfigurable processor that targets these requirements. Our processor consists of a heterogeneous array of coarse grain asynchronous cells. The architecture maintains most of the benefits of custom asynchronous design, while also providing programmability...
This paper presents a novel high-speed behavioural simulator (software-based emulator) for reconfigurable instruction cell based processors. These architectures are particularly suited to providing low-power, low-cost implementations of applications in a streaming environment, such as image signal processing, video playback, or base-band signal processing. As a result, many realistic applications...
This paper presents a novel instruction cell-based reconfigurable computing architecture for low-power applications, thereafter referred to as the reconfigurable instruction cell array (RICA). For the development of the RICA, a top-down software driven approach was taken and revealed as one of the key design decisions for a flexible, easy to program, low-power architecture. These features make RICA...
This paper presents the preliminary results of a physical placement algorithm for heterogeneous Dynamically Reconfigurable Arrays (DRA), based on a multi-objective, multi-threaded GA. The algorithm deals with the spatial and temporal nature of the configurations used in DRAs, in an attempt to find a suitable layout for a wide range of applications, since general applicability is a key criteria for...
We present a new De-Blocking Filter module fully optimised for use on a recently introduced dynamically reconfigurable, instruction cell based architecture. The module consists of a novel combination of standard software transforms alongside architecture specific techniques and aims to reduce reconfiguration overheads and increase utilisation of resources. Our proposed filter outperforms the standard...
This paper presents a physical placement algorithm, for Dynamically Reconfigurable Arrays (DRA), based on a multi-objective, multi-threaded GA implementation. The algorithm deals with the spatial and temporal nature of the configurations used in DRAs, in an attempt to find a suitable layout for a wide range of applications, since general applicability is a key criteria for DRAs. The results show that...
We present a new de-blocking filter module fully optimised for use on a recently introduced dynamically reconfigurable, instruction cell based architecture. The module consists of a novel combination of standard software transforms alongside architecture specific techniques and aims to reduce reconfiguration overheads and increase utilisation of resources. Our proposed filter outperforms the standard...
Rapid-prototyping of commercial devices and the demanding requirements for flexible hardware in mobile applications have driven the raise of reconfigurable hardware. The adaptation of CAD design tool is essential for the development of these arrays. While the performance of conventional FPGAs is limited by their predefined architecture, domain- specific reconfigurable arrays target a set of similar...
This paper presents a new baseline profile compliant H.264 decoder implementation specifically tailored for an ANSI-C programmable, dynamically reconfigurable, instruction cell based architecture which has been developed. We use the ffmpeg libavcodec library as the basis for our decoder and identify the most processor intensive functions. These functions are tailored in a novel framework incorporating...
This paper presents a new operation chaining reconfigurable scheduling algorithm (CRS) based on list scheduling that maximizes instruction level parallelism available in distributed high performance instruction cell based reconfigurable systems. Unlike other typical scheduling methods, it considers the placement and routing effect, register assignment and advanced operation chaining compilation technique...
This paper describes the architecture of our dynamically reconfigurable network-on-chip (NoC) architecture that has been proposed for reconfigurable multiprocessor system-on-chip (MPSoC), as a solution to the increased communication needs, low silicon cost, quality of service and scalability of network in mind. The novelty of the proposed NoC lies in the fact that it dynamically configures itself...
Domain-specific reconfigurable arrays have shown to provide an efficient trade-off between flexibility of FPGA and performance of ASIC circuit. Nonetheless, the design of these heterogeneous arrays is a labour intensive process. Furthermore, the manual creation of the array architecture could not have been fully optimised, hence limiting their performance. This paper presents a placement technique...
This paper presents a novel domain specific reconfigurable architecture and an associate design methodology for system-on-chip (SoC) platform which provides flexibility as well as low-power consumption. Two Viterbi decoders, which are widely used in wireless communication system, are implemented on the proposed architecture using the proposed design methodology. The measured performance shows that...
Domain-specific reconfigurable arrays are usually designed for specific applications and provide a good compromise between speed, power and flexibility. In this paper, a novel reconfigurable finite state machine (FSM) array is presented for implementing generic FSMs. Compared with commercial FPGA devices, the new architecture provides the following reductions: up to 90% in power consumption, up to...
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