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In this paper, an efficient method is proposed to accurately analyze large-scale power/ground (P/G) networks, where inductive parasitics are modeled with the partial reluctance. The method is based on frequency-domain circuit analysis and the technique of vector fitting, and obtains the time-domain voltage response at given P/G nodes. The frequency-domain circuit equation including partial reluctances...
As CMOS technology scales continually, interconnect power has become a significant part of total chip power. Without compromising performance, timing slacks can be utilized to optimize interconnect power efficiently. The optimization of total interconnect power is affected not only by the properties of each interconnect as well as the timing constraint, but also by the circuit topology. In this paper,...
In this paper, the authors propose a novel statistical model order reduction technique, called statistical spectrum model order reduction (SS-MOR) method, which considers both intra-die and inter-die process variations with spatial correlations. The SSMOR generates order-reduced variational models based on given variational circuits. The reduced model can be used for fast statistical performance analysis...
This paper describes the stochastic model order reduction algorithm via stochastic Hermite polynomials from the practical implementation perspective. Comparing with existing work on stochastic interconnect analysis and parameterized model order reduction, we generalized the input variation representation using polynomial chaos (PC) to allow for accurate modeling of non-Gaussian input variations. We...
In the process of solution evaluation for simulated annealing, the computation for wire-length is still a time consuming part, though now the buffer planning and thermal model have taken up a lot of time. And the traditional wire-length model HPWL executes in O(ntimesm) time in which n stands for the number of nets and m is the average number of the modules that the nets connect. In order to reduce...
Power dissipation problem becomes a dominant factor in the state-of-the-art IC design. Not only transistor but also interconnect should be taken into consideration in power calculation. In this paper, we use accurate delay and power models to construct buffered routing trees with considerations of delay and power optimization. Experimental results show our method can save much of buffer and power...
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