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Design and implementation of a CMOS multiphase 10b digitally controlled oscillator (DCO) in ring topology that employs fraction-based series to optimize the transistors size, are presented. One of the advantages of using fraction-based series is that it can reduce the power consumption compared to the binary series without any cost of tuning range and phase noise. The proposed DCO, which was implemented...
This paper presents a digitally controlled oscillator (DCO) in Inductor-Capacitor (LC) topology with an enhanced frequency-steps and power consumption. Using special Fibonacci sequence method for optimizing capacitor sizes, this digitally-controlled oscillator (DCO) realizes frequency-tuning steps superior than a conventional DCO using binary sequence without increasing the power consumption. The...
A 12-bit Digital-analog converter (DAC) with pseudo Fibonacci sequence was fabricated in a 0.18μm CMOS technology. Proposed 12-bit DAC is composed of a 6-bit pseudo Fibonacci sequence and 6bit unary sequence. The power consumption of the proposed DAC is expected lower than that of conventional binary and unary DAC. The simulated power consumption of proposed 12-bit DAC is 40mV at 3.3V supply voltage...
A design of high linearity (IIP3), low flicker noise (NF), high conversion gain (CG) double-balanced Gilbert-cell mixer (DBGCM) is presented. Since the performance of a direct conversion receiver (DCR) is strongly affected by linearity and flicker noise (1/f) of a mixer in receiving side, a hybrid technique of dynamic current injection (DCI), a tuned inductor in switching pair and direct superposition...
In this paper a low flicker-noise highly linear 5 GHz direct conversion receiver (DCR) has been proposed. A dynamic current injection (DCI) technique has been utilized in addition with a tuning inductor for output flicker noise (1/f) reduction. Derivative superposition (DS) technique has been used in the mixer circuit to enhance the linearity. The DCR has been designed and fabricated using TSMC 0...
An ultra-wideband low noise amplifier employs shunt resistive feedback is presented. LNA chip area has been reduced significantly using active inductor load. The LNA is designed and fabricated in the standard 0.18μm CMOS technology. The UWB LNA exhibit a measured gain of 12.5 to 13dB, and a noise figure of 3.8 dB over 1-5 GHz frequencies. S11 is less than -8dB within the entire band of frequencies...
An ultra-wide band low noise amplifier (LNA) is proposed. An UWB LNA from 3-7 GHz has been designed exploiting the wide band input matching of common gate and the high gain of cascode amplifier. The LNA has been fabricated in the standard 0.18μm CMOS process. The measured gain is 11.5dB from 3 GHz to 7 GHz, and noise figure is 3.5 dB. The measured input and output return loss is less than -11 dB of...
We proposed a method to realize the fine frequency-tuning step using tiny capacitors instead of MIM capacitors for a digitally controlled oscillator (DCO). The tiny capacitors are realized by the coplanar transmission lines in a 6 metal layers (M6) foundry of 0.18 um CMOS technology. These transmission line based capacitors are designed by using electro-magnetic field simulator, and co-designed by...
This paper presents a design methodology and verification of a 2/5 GHz dual band digitally-controlled oscillator (DCO). The presented DCO employed two spiral inductors and a switching transistor between them to operate at two bands of frequency. The switch is controlled by a digital signal so that shifting from one band of frequency to another to control the operation of spiral inductors needs no...
A digital-controlled oscillator (DCO) employing on-chip coplanar waveguide (CPW) resonator is proposed for 5 GHz-band wireless communication applications. A 10 bit DCO using on-chip designed, fabricated and tested. By comparing the measured results on the fabricated chip in 0.18 mum CMOS technology, it has noted that the proposed DCO employing on-chip CPW resonator is smaller in size and frequency-tuning...
This paper describes the design of a 3.1 to 4.8 GHz CMOS power amplifier (PA) for ultra-wideband (UWB) applications using TSMC 0.18-mum CMOS technology. The UWB PA proposed in this paper employs cascode topology with an additional common source stage to achieve high power gain. The current reused technique is implemented to enhance the gain at the upper end of the desired band for gain flatness and...
Digitally controlled LC oscillator (LC-DCO) design in 0.18 mum CMOS technology is presented with low phase noise and low power dissipation. Particular attention is given to achieve the wide tuning range. A varactor array is implemented using new logic, which made the significant reduction in the number of signal lines and the reduction in the size of local decoder, used to decode the input control...
This paper describes simulation results of high dynamic range mixer, based on resistive ring topology. Mixer is designed using TSMC CMOS 0.18um technology. This mixer downconverts RF signals in the range 2-6 GHz to low IF using LO signals below corresponding RF frequencies and perform low-pass filtering with 3dB bandwidth 33 MHz. Unlike pure resistive ring topology, mixer has a positive power gain...
This paper presents a simple architecture for 8-bit digital controlled oscillator (DCO) on 3-stages ring topology in TSMC 0.35 mum CMOS technology. A new schematic of tristate inverter is also proposed. The proposed tristate inverter has higher switching speed and low power consumption as compared to conventional one. The control digit changes the driving current that provides large tuning range from...
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