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SONOS devices using gate injection programming and erasing have better cycling endurance because the gate oxide is not stressed by P/E operations. This work studies the gate injection behavior in detail using the recently developed gate-sensing and channel-sensing (GSCS) technique. GSCS accurately locates the charge centroid during programming/erasing and reliability tests. For the first time, we...
Barrier engineered charge-trapping NAND flash (BE-CTNF) devices are extensively examined by theoretical modeling and experimental validation. A general analytical tunneling current equation for multi-layer barrier is derived using WKB approximation. The rigorously derived analytical form is valid for both electron and hole tunneling, as well as for any barrier composition. With this, the time evolution...
The high-Vt state data retention of 2bit/cell SONOS using hot-hole erasing method is studied extensively using a 0.13 mum virtual-ground array NOR-type test chip. We design various trap-layer engineering using multi-layer stacks of SiN and SiON in order to change the intra-nitride conduction. However, our results show that the post-cycled retention is insensitive to the trap-layer engineering. Next,...
Using a recently developed gate-sensing and channel- sensing (GSCS) transient analysis method, we have studied the detailed charge-trapping behavior for SONOS-type devices. By adding gate sensing to the conventional channel sensing, the two variables (total charge Qtot and mean vertical location x circ) can be solved simultaneously. By using this powerful new tool on several SONOS-type structures,...
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