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Metal gate/high-k LSTP CMOSFETs for sub-32nm technology was demonstrated using a novel-damage free neutral beam-assisted atomic etching process. Due to its neutralized atomic flux and chemical reaction, it had a high etch selectivity, oxygen concentration control and improved device performance/reliability. NBALE is a key process for reducing GIDL and Ioff control which is a key factor for LSTP.
We report the results of a systematic study to understand low drive current of Ge-based nMOSFET. The poor electron transport property is primarily attributed to the intrinsically low density of state and high conductivity effective masses. Results are supported by interface trap density (Dit) and specific contact resistivity (rhoc), which are comparable (or symmetric) for both n- and p-MOSFETs. Effective...
We have developed a novel dual phase-modulated Ni silicide for Schottky barrier and series resistance reduction in dopant-segregated source/drain (DSS) n-MOSFETs. Using pre-silicide N2+ implant (thereafter N-implant), it is possible to selectively form interfacial epitaxial Si-rich NiSi2, reducing electron Schottky barrier(SB) from 0.7 eV to 0.34 eV while maintaining a low resistive bulk NiSi, at...
We have studied key parameters for controlling threshold voltage (Vth) variation and strain maintenance of gate first SiGe channel pMOSFETs. By overcoming 1) Ge diffusion and 2) strain relaxation during source/drain activation, we for the first time demonstrate high Ge% (50%) SiGe channel with millisecond flash anneal. Optimizing the thermal budget with millisecond anneal keeps the Vth variation same...
We report on new observations of hot carrier (HC) degradation in strained Si/Si1-xGex(x = 0.2 to 0.5) p-MOSFETs. By using low voltage current-voltage measurement coupled with carrier separation, we are able, for the first time, to easily distinguish the energy distribution of the interface traps. High-K dielectrics on SiGe p-channel show higher interface traps generation located close to conduction...
A novel stress-anneal approach has been investigated to separate the role of electrons and hole charge trappings in Hf-based gate oxides. It is observed that heat treatment following a stress experiments on Hf-based MOSFET can effectively eliminate electron trapping in the oxide. We also report that hole accumulation in the bulk of the Hf-based dielectrics is primarily responsible for dielectric breakdown,...
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