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An on-chip protection against IEC 61000-4-2 discharges is presented. The protection level is tested by means of HMM stress. The failure signature is identified by means of TLP testing and physical failure analysis. It is shown that it is possible to accurately predict the HMM failure level by means of a simplified circuit model, calibrated by means of 100 ns TLP data.
Unexpected functional failures were found in the core of an IC, processed in a 65 nm technology with 1.8 nm gate oxide after MM testing, although a comprehensive rail-based protection scheme was applied. Failure analysis was performed including Obirch, backside de-processing, and SEM analysis to locate the failure in the gate oxide of several core NMOS transistors. Careful TLP measurements on NMOSTs...
We define rules to reduce the ESD test complexity for chips with large pin count. These rules exploit the structural similarity in the pad-ring and have a long history of use without bad experiences. Using these rules an automated software tool can be developed for reduced ESD test generation.
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