The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
We present a compact model that provides a quick estimation of the stress and mobility patterns around arbitrary configurations of Through-Silicon Via's (TSVs). No separate TCAD simulations are required for these configurations. It estimates nFET and pFET mobility for industry-standard as well as for (100)/<;100>; substrate orientations. As the model provides mobility info in less than 0.1 millisecond/transistor/TSV,...
This paper is the first to provide a comprehensive study on the layout dependence of scaled Si1-xGex-channel pFETs. Drive current enhancement up to 90% is demonstrated for Si0.55Ge0.45-channel pFETs with LG = 35 nm and EOT = 0.9 nm when the transistor width (W) is scaled from 10 μm to 110 nm. This is attributed to a change in channel stress from biaxial compressive at large W to the more beneficial...
For the first time, an STI module is integrated in an advanced 70 nm Ge-pFET technology allowing EOT scaling down to 0.85 nm. Gate leakage is kept below 0.2A/cm2 and ION is increased inversely proportional to the EOT. The impact of this aggressive EOT scaling on hole mobility is also investigated by temperature measurements down to 4 K, suggesting the presence of defects at different levels of the...
This paper is the first to quantify drain extension leakage in a sub-100-nm gate-length bulk germanium technology. Leakage through the transistor's extension/halo junction is shown to be the dominant leakage component in a scaled transistor layout. Optimizing halo and extension implants to improve short-channel control further increases the extension leakage. As a consequence, drain-to-bulk leakage...
This report presents high-k poly ring oscillators with a performance of tau=16.2 ps/st at 6E-6A/st for Lg=80 nm. This was achieved by using a SiGe channel for nFET and pFET. A minimum device length of 50 nm was built by using this technique. The transistors reach Ion=120 muA/mum at Ioff=20 pA/mum with Tinv=2.4 nm, resulting in a normalized delay of 8.7 ps (Vdd=1.0 V). This is the best high-k poly...
This paper demonstrates for the first time the integration of an HfO2/TiN/poly gate stack and a recessed SiGe S/D module. It also shows that by combining the SiGe stressor with a compressive nitride contact etch stop layer, it is possible to reach improvements in IDSAT of up to 65%, showing that the various strain mechanisms are additive on advanced gate stacks. This way an IDSAT of 422 muA/mum at...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.