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The K-Nearest Neighbor (K-NN) algorithm is one of the most common classification algorithms and widely used in pattern recognition and data mining. K-NN hardware acceleration is necessary for applications with massive high-dimensional data. High level synthesis (HLS) is an increasingly adopted technique in digital circuit design, which can help to raise the abstraction levels. In this paper, we exploit...
In modern commercial FPGA EDA tools, modular design is very common to reduce the development time. This paper introduces a new method of modular design and module connection based on relocatable P&R constraints, where users can build their own module library and invoke these modules easily. A routed file from the module library can be directly used as a module which can be placed in the user-specified...
Most FPGAs use Look-Up Table (LUT) as the basic logic block. Input sharing look-up table (ISLUT) architecture is a cluster architecture, which can be configured as one 6-input LUT, two smaller LUTs or other modes. In this paper, several ISLUT architectures are added into Verilog-to-Routing (VTR) tool to compare with standard 6-input basic logic element (BLE6) architecture. Experimental results show...
RM (Reed-Muller) expansions have shown advantages compared with the traditional SOP (Sum-of-Products) forms in the areas of arithmetic logic, reversible logic synthesis and Boolean quantum circuit design. A new algorithm is presented for the conversion between SOP and RM forms of multiple output functions. This procedure is based on the cube set expressions and therefore independent on number of input...
This paper mainly discusses online tasks scheduling problem on hybrid CPU-FPGA reconfigurable systems. In these systems, hybrid tasks may be binary codes executed on CPU as well as hardware logic circuits implemented on FPGA. Tasks scheduling algorithms of conventional operating systems are not suitable for scheduling hybrid tasks on CPU-FPGA architecture. Based on a real reconfigurable system prototype,...
Efficient task scheduling is very important for obtaining high performance in reconfigurable computing system. Previous researches mostly concentrate on the spatial placement of tasks, and did not pay enough attention to temporal factors. This paper focuses on the on-line scheduling of real-time tasks with known executing time, and introduces the notion of recognition-complete for scheduling algorithms,...
Modeling is an efficient way to improve SoC design efficiency. In this paper, a Model Driven Architecture (MDA) based approach is proposed to combine the capability of newly released Unified Modeling Language 2.0 (UML) with SystemC, extending UML to express SystemC concept while maintaining the mappings between them. This approach will consequently promote stepwise semiautomatic conversion from UML...
With the improvement of SoC design flow, early system prototype is an efficient way in which designers can find function bugs and performance limitations. The SystemC transaction-level model, a high level system model, has been attracted great attentions in embedded system design community. In this paper, we present a system prototype methodology, its corrective modeling technique and development...
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