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This paper presents a sub-0.3V CMOS full-wave rectifier for energy harvesting devices. By adopting a body-input comparator with simple bias circuit and body bias technique, the lowest input voltage amplitude can be reduced to 0.28V when using a standard CMOS 0.18µm process. The voltage drop of negative voltage converter can be reduced to enhance the output voltage by the body bias technique. In combination...
With the advent of nanometer age in digital circuits, the overshooting time becomes a dominating component of gate delay for CMOS logic gates. Till now, few researches have focused on the overshooting effect of multi-input gate. Therefore, in this paper, an effective model considering the overshooting effect of multi-input gate is presented. The experimental results using 32nm PTM model reflect that...
In Static Timing Analysis, the conventional methods usually use an iterative method to ensure the accuracy of the effective capacitance Ceff, which is usually used to compute the delay of gate with interconnect load and to capture the output signal shape of the real gate response. In this paper, a polynomial approximation method is used to make the nonlinear Ceff equation be solved without iterative...
With the scaling of complementary metal-oxide-semiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacitance has more significant influence on CMOS gate analysis, especially on CMOS gate static timing analysis. In this paper, the overshooting effect is modeled for CMOS inverter delay analysis in nanometer technologies. The results...
In this paper, a four-phase all PMOS charge pump based on the voltage doubler structure is proposed. The proposed charge pump is designed in 1.8 V 0.18 mum standard CMOS process with high voltage boosting efficiency and little output ripple. Moreover, it solves the voltage overstress problem which exists in the conventional charge pump and eliminates the body effect as well by means of adding two...
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