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In the context of efforts to achieve zero emissions of carbon dioxide, wake-up circuits have attracted attention as a promising approach for reducing standby power. The dominant consumers of standby power are household electric appliances driven by AC power such as TVs. In these appliances, power is lost at an AC-DC converter even when the appliances are turned off. Although an infrared remote controller...
The paper presents a single-chip application and dual-mode baseband processor. It features triple V design - a technology in a low-power 65nm CMOS process that achieves 500MHz for two CPUsp; power domains are separated into 21 sub-blocks to reduce leakage power; introduces a new IP-MMU, which translates virtual address to physical address or physical address to physical address, to 17 different kinds...
A single-chip 11.15times11.15mm2 application and dual-mode WCDMA/HSDPA and GSM/EDGE baseband processor achieves 390MHz in triple-V, low-power 90nm 8M CMOS. A CPU core standby mode with resume cache reduces leakage current of each CPU to 0.04mA when idle. A dynamic bus clock-stop scheme further reduces power consumption. Interconnect buffers allow the chip to support 30f/s VGA video.
High performance CMOSFET technology for 45nm generation is demonstrated. The key device strategies for junction scaling, gate stack scaling and stress-induced mobility enhancement are discussed. Reversed-order junction formation improves short channel effect (SCE) drastically. Novel SiON with improved poly-Si gate depletion improves the drive current by 8%. The systematic study on the process-induced...
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