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This document proposes a new mathematical model of a solar cell that can be implemented in various software platforms. The model is based on an hyperbolic tangent function and linear equations for short circuit current, open circuit voltage and saturation conductance. It incorporates the irradiation and temperature effects and fits to the physical solar cell behavior by measuring the currents and...
This document exposes the architecture and performance of an improved Maximum Power Point Tracking (MPPT) circuit, applied to a high power solar cell. The circuit uses event-based control, such that the solar cell power oscillates between maximum value and a limit falling factor of its maximum. The circuit is composed in general by analog components as comparators, switches, attenuators and incorporates...
This paper presents a level-shifting technique for high-voltage power converter applications. The proposed circuit effectively combines capacitive and active coupling of the input low (high) side signal to the output high (low) side to reduce the propagation delay of the level-shifting operation. By using the resulting circuit, (i) the high-side PMOS switch is driven at high speed and (ii) a quasi-zero...
Data converters are essential gateways leading an analog signal into a digital format. Data converters are more and more important for electrical and optical communication systems where the analog signals must be transformed in analog at the very beginning of the processing chain. The use of advanced modulation schemes lead to a pressing request for power efficient A/D converters operating with a...
This paper presents design and experimental results of a second-order, discrete-time, quadrature band-pass ΣΔ modulator targeted for wireless body area networks. The non-conventional architecture locks the intermediate frequency (IF) to the sampling frequency. Measurement results collected from a CMOS 0.18-μm prototype achieves a peak SNR of 55 dB over 100-kHz bandwidth and 40-dB SNR over 2.6-MHz...
In this paper a readout circuit for label-free DNA detection based on piezo-resistive MEMS cantilevers is presented. The circuit is designed to have high sensitivity and a precise calibration block in order to deal with possible large variation of the cantilever resistance due to technological mismatch effects. The readout channel has been electrically tested showing, as preliminary results, a total...
Optimal matching between tag antenna and integrated circuit is crucial for maximizing delivered power in remotely-powered sensor systems. The method maximizes conjugate matching between antenna with inductive reactive impedance and an integrated circuit with capacitive reactive impedance. Obtaining the desired conjugate impedance by the intrinsic antenna impedance excludes the need of an impedance...
The successive-approximation (SA) algorithm is traditionally used for low bandwidth applications because it requires n clock cycles or more to obtain n-bit resolution. However, the use of modern nanometer CMOS technologies and special design solutions overcome the speed limit, enabling conversion rates in the hundreds of MHz with very low power consumptions. This design uses the successive-approximation...
This third-order ΔΣ modulator, suitable for high-resolution low-power sensor systems, consumes 140μW to obtain 84dB SNDR with OSR=16 and 100kHz signal bandwidth. The achieved FoM is 54fJ/conversion-step. The DACs use a single resistive divider to generate 32 differential 5b reference voltages. The proposed scheme totally cancels the error caused by gradient in the resistance values. Resistor sizes...
This paper presents a methodology to design and to optimize inductive power link for biomedical applications. The importance of the operation frequency on the application is expressed. A model of inductive link is presented. The dimensions of the coils are compatible with the size of a mouse and the mouse cage. The simulation results are in good agreement with the analysis.
An 11b 60MS/s 2-channel two-step SAR ADC in 65nm CMOS is presented. The scheme shares the op-amp between channels for the residual generation and takes advantage of time interleaving for reusing the input S&H of the first stage. A reduction of the gain in the residual generator and sub-threshold operation enables the use of a power-effective, singlestage op-amp with 69dB-gain. The ADC achieves...
In this paper we present a MASH bandpass ΣΔ modulator for WCDMA applications. The signal bandwidth of the proposed modulator is 10 MHz, centered around an intermediate frequency (IF) of 70 MHz. Each ΣΔ modulator of the MASH structure is based on a two-path architecture, which allow us to obtain the desired in-band noise shaping zeros and reduce the power consumption. The ΣΔ modulator is implemented...
A fully digital feedforward ΣΔ modulator is described. The technique, here applied to a second order low-pass modulator, strongly reduces the operational amplifiers output swing, thus allowing the use of power effective single stage architectures. The method enables reduced slew-rate requirements and allows operation at lower power supply voltages. The proposed technique has better or comparable performance...
This paper presents a new solution to obtain a spurs-free high precision amplifier. The method involves input chopping and correlated double sampling signal de-chopping. The offset is removed by using DC coupling. The proposed method, verified with transistor level simulations, is applied to a rail-to-rail input amplifier with 187 dB DC gain and 13.7 μA current consumption.
This paper presents an All Digital PLL (ADPLL) based on a first order noise shaping Time-to-Digital Converter (TDC). The architectures of two state-of-art ADPLLs and a state-of-art Gated Ring Oscillator (GRO) TDC are described. The architecture of the GRO TDC is compared with that of the proposed Local Oscillator based TDC (LO TDC) in terms of spectral performance. Behavioral Verilog-AMS models of...
A novel multi-rate Time-Interleaved Current Steering Digital to Analog Converter with unity element sharing is presented. Proposed 12-bit DAC is simulated in 90nm CMOS technology. The implemented DAC is divided to two segments, MSB and LSB segments, each having 6 bits of resolution. Taking advantage of the oversampling requirement due to the reconstruction filter at the DAC output, the MSB segment...
A double sampled second order ΣΔ modulator with an analog look ahead (ALA) approach is presented. The proposed architecture provides an extra clock period to be used for the quantization. The feedforward path in both integrators allows the further reduction of the output voltage swing, relaxing also the slew-rate requirements of the op-amps. Moreover, the modulator enables the reduction of the number...
A chopper ripple-free circuit with input noise density of 37 nV/√Hz is presented. The CMOS scheme chops the input and demodulates the result after amplification with CDS. Offset temperature dependence is better than 0.03 μV/°C. The analog current consumption is 12.8 μA with supplies ranging from 1.8 V to 5 V. The noise efficiency factor is 5.5.
A nested digital delta-sigma modulator (DDSM) architecture for fractional-N frequency synthesis is investigated and compared with the conventional MASH 1-1-1 DDSM. In the nested architecture, the LSBs of the input word are processed by a first-order DDSM and added to the MSBs before being processed by a third-order DDSM. Using the error masking design methodology [1], rules for selecting the optimum...
A method for a smart selection and sequencing of unity capacitors in a multibit DAC is proposed. The approach, suitable for the DAC nonlinearity correction in sigma-delta modulators, obtains results that are better than the dynamic element matching. Key of the technique is an off-line self-measurement of mismatches. The results significantly improve when the DAC capacitors are selected from a set...
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