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A new panel base package (PBP) technology that was developed based on the concepts of the wafer level package (WLP) has been proposed in order to obtain the signal fan-out capability for the fine-pitched integrated circuit (IC). In the PBP, the chip is attached to a selected chip carrier, and the volume of IC devices is extended for the redistribution of the original die pads. In this study, the thermal...
The wafer level package (WLP) is a cost-effective solution for the electronic package, and has been increasingly applied during recent years. In this study, a new packaging technology developed based on the concepts of the WLP, the panel base package (PBP) technology, is proposed in order to further obtain the capability of signals fan-out for the fine-pitched integrated circuit (IC). In the PBP,...
In this study, a new packaging technology, chip-on-metal (COM) panel level package (PLP), is proposed to resolve the problem of assembling a fine-pitched chip to a coarse-pitched substrate. During the manufacturing process, the filler polymer material is selected to fill the trench around the chip and provide a smooth surface for the redistribution lines. Therefore, the solder bumps could be located...
In this study, a chip-on-metal wafer level package (CoM-WLCSP) with stacking and fan-out capabilities, and a package-on-package (PoP) structure using this CoM-WLCSP are proposed. Moreover, the concept of the CoM-WLCSP and the process of fabricating this novel WLCSP are described. The parametric analysis of the CoM-WLCSP in board level is also studied by using the three-dimensional finite element model...
A novel solder on rubber (SOR) structure of the advanced wafer level chip scaled packaging (WLCSP), having the capability of releasing the deformation energy which is caused by the CTE mismatch between the silicon chip and the substrate, is proposed herein. In the SOR structure, a metallic trace and solder pad would be formed on the rubber-based polymer, and a solder is attached onto the said pad...
As electronic devices become more complicated and the need for semiconductor chips in portable products increases, the demand for smaller and lighter chips and packages becomes greater. However, because of the different temperature loading from the manufacturing process, the mismatch in the coefficient of thermal expansion (CTE) between different materials affects the packaging reliability. In this...
A novel wafer level chip scaled packaging (WLCSP) having the capability of the redistributing the electrical circuit is proposed herein to resolve the problem of assembling a fine pitched chip to a coarse pitched substrate. In the fan-out WLCSP, the chip is first attached to a specific 8" chip carrier, and then the trench between the chips are filled by the filler polymer. The solder bumps could...
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