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Modern NAND flash memory chips provide high density by storing two bits of data in each flash cell, called a multi-level cell (MLC). An MLC partitions the threshold voltage range of a flash cell into four voltage states. When a flash cell is programmed, a high voltage is applied to the cell. Due to parasitic capacitance coupling between flash cells that are physically close to each other, flash cell...
Crossbars are a basic building block of networks on chip that can be used as fast, single-stage networks or in router cores for larger scale networks. However, scaling crossbars to high radices presents a number of efficiency, performance, and area challenges. Thus, we propose modular flow-through crossbar switch cores that perform better at high radices than conventional monolithic designs. The modular...
A myriad of security vulnerabilites can be exposed via the reverse engineering of the integrated circuits contained in electronics systems. The goal of IC reverse engineering is to uncover the functionality and internal structure of the chip via techniques such as depackaging/delayering, high-resolution imaging, probing, and side-channel examination. With this knowledge, an attacker can more efficiently...
Despite best efforts, integrated systems are “born” (manufactured) with a unique ‘personality’ that stems from our inability to precisely fabricate their underlying circuits, and create software a priori for controlling the resulting uncertainty. It is possible to use sophisticated test methods to identify the best-performing systems but this would result in unacceptable yields and correspondingly...
Side channel attacks exploit inadvertent information leakage from the physical implementation of computing systems, bypassing the theoretical strength of cryptographic algorithms. Of particular concern are software side-channel attacks which can be mounted remotely without access or alteration of the hardware system. One type of attack that has been demonstrated to be highly effective is cache timing...
The implementation of the SubBytes (or S-Box) step of the AES algorithm significantly contributes to the area, delay, and power of AES accelerators. Unlike typical logic gate S-Box implementations, we use full-custom 256×8-bit ROMs, which significantly improve performance and efficiency. We implemented a fully-unrolled, pipelined AES-128 encryption accelerator using ROM-based S-Boxes in 65nm bulk...
As process technologies have scaled, the increasing number of processor cores and memories on a single die has also driven the need for more complex on-chip interconnection networks. Crossbar switches are primary building blocks in such networks-on-chip, as they can be used as fast single-stage networks or as the core of the router switch in multi-stage networks. While crossbars offer non-blocking,...
Creating backdoors in integrated circuits (ICs), stealing hardware intellectual property, counterfeiting electronic components, reverse engineering ICs, and injecting malware in ICs are no longer nation state acts requiring specialized, expensive, and unlimited resources. Democratization of IC design has created numerous opportunities for rogues throughout the IC supply chain to inflict these attacks...
Hardware true random number generators are an essential functional block in many secure systems. Current designs that use bi-stable elements balanced in the metastable region are capable of both high randomness and high bitrate. However, these designs require extensive support circuits to maintain balance in the metastable region, complex built-in self test loops to configure the support circuits,...
Differential power analysis (DPA) has been shown to be a highly effective and easy to mount side-channel attack. One effective method of increasing DPA resistance is to use three-phase dual-rail pre-charge logic (TDPL), but this type of logic is vulnerable to manipulation of the clock generation/distribution hardware. If an attacker can slow down the clock, separate the evaluate phase from the discharge...
Computer architects are increasingly interested in evaluating their ideas at the register-transfer level (RTL) to gain more precise insights on the key characteristics (frequency, area, power) of a micro/architectural design proposal. However, the RTL synthesis process is notoriously tedious, slow, and errorprone and is often outside the area of expertise of a typical computer architect, as it requires...
Most existing packet-based on-chip networks assume routers have buffers to buffer packets at times of contention. Recently, deflection-based bufferless routing algorithms have been proposed as an alternative design to reduce the area, power, and complexity disadvantages associated with buffering in routers. While bufferless routing shows significant promise at an algorithmic level, these algorithms...
Retention errors, caused by charge leakage over time, are the dominant source of flash memory errors. Understanding, characterizing, and reducing retention errors can significantly improve NAND flash memory reliability and endurance. In this paper, we first characterize, with real 2y-nm MLC NAND flash chips, how the threshold voltage distribution of flash memory changes with different retention age...
Despite best efforts, integrated systems are “born” (manufactured) with a unique ‘personality’ that stems from our inability to precisely fabricate their underlying circuits, and create software a priori for controlling the resulting uncertainty. It is possible to use sophisticated test methods to identify the best-performing systems but this would result in unacceptable yields and correspondingly...
Physical unclonable functions (PUFs) are primitives that generate high-entropy, tamper resistant bits for use in secure systems. For applications such as cryptographic key generation, the PUF response bits must be highly reliable, consistent across multiple evaluations under voltage and temperature variations. Conventionally, error correcting codes (ECC) have been used to improve response reliability,...
The embedded memory hierarchy of microprocessors and systems-on-a-chip plays a critical role in the overall system performance, area, power, resilience, and yield. However, as process technologies scale down to nanometer-regime geometries, the design and implementation of the embedded memory system are becoming increasingly difficult due to a number of exacerbating factors including increasing process...
As NAND flash memory continues to scale down to smaller process technology nodes, its reliability and endurance are degrading. One important source of reduced reliability is the phenomenon of program interference: when a flash cell is programmed to a value, the programming operation affects the threshold voltage of not only that cell, but also the other cells surrounding it. This interference potentially...
Physically Unclonable Functions (PUFs) are structures with many applications, including device authentication, identification, and cryptographic key generation. In this paper we propose a new PUF, called SCAN-PUF, based on scan-chain power-up states. We argue that scan chains have multiple characteristics that make them uniquely suited as a low-cost PUF. We present results from test chips fabricated...
While SRAM and DRAM are often assumed to have very small data retention times (bits are lost immediately at power-down) and no data remanence (stored bits leave no traces even after a prolonged storage period), under some conditions these assumptions do not hold. Both retention and remanence have been exploited by malicious attackers to compromise system data and encryption keys in secure systems...
Physical Unclonable Functions (PUFs) are security primitives used in a number of security applications like authentication, identification, and secure key generation. PUF implementations are evaluated on their security characteristics (uniqueness, randomness, and reliability), as well as conventional VLSI design metrics (area, power, and performance). We compare bi-stable based PUFs (SRAM and sense...
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