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It is our privilege to welcome you to the 44th IEEE International Test Conference (ITC) sponsored by the IEEE Computer Society and the Philadelphia Section. We are pleased to once again return to the Disneyland Resort Hotel in Anaheim, California - a great venue for ITC, the world's premier conference in test.
With shrinking geometries of PCBs, increasing interface speeds and corresponding loss of test point access to diagnose structural test defects, new standard test mechanisms are needed to test chip-to-chip connectivity and functionality at the board level. New requirements for an integrated circuit ‘BA’ (Board-Assist) BIST to structurally test these interfaces will be presented. A standardized BA-BIST...
An Integrated Circuit (IC) can be reverse engineered by imaging its layout and reconstructing the netlist. IC camouflaging is a layout-level technique that hampers imaging-based reverse engineering by using, in one embodiment, functionally different standard cells that look alike. Reverse engineering will fail if the functionality of a camouflaged gate cannot be correctly resolved. We adapt VLSI testing...
As the supply chain of electronic circuits grows more complex, with parts coming from different suppliers scattered across the globe, counterfeit integrated circuits (ICs) are becoming a serious challenge which calls for immediate solutions. Counterfeiting includes re-labeling legitimate chips or illegitimately replicating chips and deceptively selling them as made by the legitimate manufacturer,...
A contactless TSV probe based on the principle of resonant inductive coupling is presented in this work. The proposed scheme allows TSV data observation up to 2Gbps when the probe and TSV are 15μm apart.
Running at-speed functional tests has shown to be a very effective method to detect faulty chips. In our previous paper we presented a methodology for generating functional tests aimed at hard to detect gate level faults in the control logic of a processor. In that methodology gate level tests were mapped to the register transfer level (RTL) and a faulty RTL model was built. The propagation constraints...
SNR enhancement of a 6-band WCDMA/ HSDPA+ directconversion transceiver supporting 21 Mbps High Speed Downlink Packet Access Evolved (HSDPA+) in a single CMOS die is evaluated in this paper. The paper mainly focuses on enhancing SNR performance of a WCDMA/HSDPA+ receiver by minimizing the error vector magnitude (EVM) with the digital compensations of the amplitude and group delay variations of the...
We present a distributed-multicore hybrid ATPG system which leverages the computing power of multiple machines each with multiple CPUs. The system is versatile and scalable and supports flexible configuration. Experimental results are compared to a highly efficient multicore ATPG system.
A realistic, as opposed to fixed pessimistic end-of-life method to identify paths that are at-risk to excessive degradation due to aging is presented. It uses library cell grading information to assess the cells/instances for their sensitivity to parametric degradation.
Diagnosing functional failures in complicated electronic boards is a challenging task, wherein debug technicians try to identify defective components by analyzing some syndromes obtained from the application of diagnostic tests. The diagnosis effectiveness and efficiency rely heavily on the quality of the in-house developed diagnostic tests and the debug technicians' knowledge and experience, which,...
The paper describes clock gating structures in practice that can impact the testability and cause silicon failure due to the race condition or timing uncertainty such as voltage droop and the process variations. The design rule check (DRC) algorithm is presented to efficiently and robustly identify such problematic structures. Furthermore, the automatic test pattern generation (ATPG) method is proposed...
Wide I/O poses serious challenges due to the requisite high density of electronics and relays near the DUT, as well as high bandwidth. A 2×2mm MEMS switch has been demonstrated, offering >80% footprint reduction relative to a typical TO-can electromagnetic relay. A further benefit of its small size, the MEMS relay is able to operate up to Ka-band (40 GHz) with hot switch capability and repeatability...
In this paper, we will present two different applications of “test pattern sampling” for logic testing that have significantly improved test cost for Processors and SOCs/ASICs at IBM. The drivers and implementations for these two methods were completely different - one relying on real-time analysis/optimization applied at wafer test; the other based on off-line analysis with daily updates and real-time...
A new threshold voltage variation monitoring circuit is introduced which utilizes a stochastic comparator group. It occupies minimal area, only requires a DC input stimulus voltage, and performs digital DC measurement. Traditional methods have required the measurement of the variation in a ring oscillator frequency. Our method circumvents the need for AC measurements, and accelerates the accumulation...
Parallel programming is an attractive solution to accelerate test pattern generation (TPG); however, the associated non-determinism often leads to non-reproducible test pattern sets. In this paper, the circular pipeline processing (CPP) principle is proposed to facilitate deterministic parallel TPG. CPP preserves the task processing orders that are necessary to ensure TPG determinism with low inter-thread...
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