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This paper presents an analysis of the bipolar effect in triple-gate n- and p-SOI devices with high-k/TiN metal gate. High-k dielectrics and thicker TiN achieve a larger trigger voltage. However, a reduced program window is found for MuGFETs with high-k dielectrics. p-FET devices give rise to a smaller sense margin and program window due to the reduced hole mobility. Narrow fin devices exhibit a larger...
SOI multiple-gate devices (MuGFETs) have shown to be promising choices to continue scaling. The devices show excellent gate control and thus reduced short-channel effects. Additionally, by using high-k dielectrics a gate leakage current reduction can be achieved. The incorporation of nitrogen into these high-k materials can improve their thermal stability, reduce the dopant penetration and allow further...
In this work, the possibility of achieving low Vt nMOS FinFET transistors through the use of a La2O3 dielectric cap, and the ability of co-integrating La2O3 capping with medium and low Vt pFinFET devices are investigated. A significant improvement in device performance was shown for thin La2O3 capping with CVD TaN electrode.
In this paper, we investigate the potentialities and properties of HfSiO/MG/cap/TiN gate stack devices, first by identifying the impact of the TiN thickness and its deposition procedure on the device characteristics, and by exploring the use of TaN vs. TiN as the 1st metal layer (MG). Deeper insight into the caps (e.g., Dy) diffusion mechanism is gained by: a) demonstrating stronger diffusion dependence...
In this paper, we investigate the dependence between the performance of multiple-gate FETs (dasiaMuGFETspsila) and the thickness of their plasma-enhanced-ALD (PE-ALD) TiN gate electrode. We show that very thin PE-ALD-TiN gate electrodes allow improved short channel effect (SCE) control and enhanced performance in n-channel MuGFETs without mobility modification. Based on the electrical characterization...
While the potential of FinFETs for large-scale integration (LSI) was demonstrated before on relaxed device dimensions, in this paper we present performance data of aggressively scaled transistors, ring oscillators and SRAM cells. FinFET SRAMs are shown to have excellent VDD scalability (SNM=185 mV at 0.6 V), enabling sub-32 nm low-voltage design.
We report, for the first time, a comprehensive study on various capping integration options for WF engineering in MuGFET devices with TiN gate electrode: HfSiO/cap/TiN, cap/HfSiO/TiN and HfSiO/TiN/cap/TiN vs. reference deposition sequence HfSiO/TiN (cap = Al2O3 for pmos, and Dy2O3 or La2O3 for nmos). We show that: 1) low-VT values (Lt 0.3 V) are achieved for both nmos and pmos, with excellent process...
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