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In this paper we propose a decoding architecture for turbo-like decoding algorithm of a particular class of Low-Density Parity Check codes. We define a methodology to design codes. In a first step a hardware architecture and the decoding scheduling are first selected. Then rules for the design of these codes are derived, aiming at improving the convergence of the decoding algorithm, while fitting...
In this paper we address the problem of flexibility of LDPC decoders in terms of coding rates. The paper introduces a code construction based on structured LDPC codes. The design of the code is performed in close relation with a targeted architecture in order to facilitate implementation at later stage. The proposed solution is based on the transformation of the parity check matrix resulting in a...
This paper investigates cycle and distance properties of structured low density parity check (LDPC) codes based on circulant permutation matrices. A very simple algorithm to detect and construct codes with good cycle properties is proposed. A geometrical approach to design codes with good girth properties is then presented and illustrated, through the definition of rules for the design of parity check...
This paper proposes a code design method for a particular class of serial concatenated codes named systematic with serially concatenated parity (S-SCP) codes. Using a particular family of S-SCP codes based on quasi cyclic code, we propose a code design taking into account both implementation and performance requirements. This design enables a particular scheduling of the decoding process enabling...
The proposed circuit computes the difference between two rectangular blocks of pixels at a maximum rate of 54 MHz. It has been designed by using rapid prototyping methods that involve both high-level behavioural language for architecture implementation and standard-cells and layout generators for layout design. The core of the circuit is a programmable delay line of 432??32 bits length implemented...
This paper describes the design and implementation of a digital video ASIC (Application Specific Integrated Circuit) that performs the line interpolation of the missing color samples of a digitized MAC (Multiplex Analog Componant) video signal. The main part of this circuit is a specific 864??8 bits memory designed as a double chroma digital delay line. The design is based on 2 micron double metal...
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