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The ESD robustness on different device structures and layout parameters of high-voltage (HV) NMOS has been investigated in 40-V CMOS process with silicon verification. It was demonstrated that a specific structure of HV n-type silicon controlled rectifier (HVNSCR) embedded into HV NMOS without N-drift implant in the drain region has the best ESD robustness. Moreover, due to the different current distributions...
In this paper, the long-pulse transmission line pulsing (LP-TLP) system is proposed to simulate the influence of cable discharge event (CDE) on integrated circuits. The layout dependence on CDE robustness of gate-grounded NMOS (GGNMOS) and gate-VDD PMOS (GDPMOS) devices has been experimentally investigated in detail. All CMOS devices with different device dimensions, layout spacings, and clearances...
Cable discharge event (CDE) has been the main cause which damages the Ethernet interface in field applications. The transmission line pulsing (TLP) system has been the most popular method to observe electric characteristics of the device under human-body-model (HEM) electrostatic discharge (ESD) stress. In this work, the long-pulse transmission line pulsing (LP-TLP) system is proposed to simulate...
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