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Increasing process variation can significantly degrade the write-ability of an SRAM. In this paper, we propose negative bit- line voltage technique to improve cell write-ability without using any on-chip or off-chip negative voltage source. Capacitive coupling is used to generate a transient negative voltage at the low bit-line during write operation. Simulations in 45 nm PD/SOI technology show a...
A methodology for evaluation and optimization of quantization error when porting a pre-existing planar design to FinFET technology is presented. A 52-bit adder from a general purpose processor is used to illustrate the key findings of this study.
A framework for accurately determining the device currents in trapezoidal FinFET devices is presented. The analytical formulation also computes the equivalent threshold voltage of an ideal rectangular fin with iso-current characteristics. The approach easily lends itself to the sensitivity analysis of device currents to variations in the geometric parameters.
A novel 3D computational self-consistent electro-thermal modeling methodology is developed to more precisely analyze leakage currents in nanoscale FinFET devices. The coupled electro-thermal modeling is applied to compare the device performance of poly-Si gate and metal-gate DG-FinFET. Results show very high leakage current in band-edge metal-gate device and poly-Si gate device. Mid-gap metal-gate...
The authors describe the first experimental result of a high-speed low-power ECL-based AC-coupled complementary push-pull circuit. Implemented in a 0.8 mu m high-performance fully complementary bipolar technology with 50 GHz n-p-n transistors and 13 GHz p-n-p transistors, a power-delay product of 34 fJ (23.2 ps at 1.48 mW) has been achieved compared with 67 fJ (45 ps at 1.48 mW) for the n-p-n only...
A non-quasi-static (NQS) model accounting for intrinsic carrier propagation delays in both B/E and B/C junctions is implemented in the ASTAP circuit simulator to evaluate the impact of non-quasi-static effects in saturated bipolar circuits. It is shown that while the extra delay introduced by the NQS effects during the turn-on transition is primarily due to the normal mode B/E NQS time constant, the...
The author presents a high-speed low-power NTL (non-threshold-logic)-based push-pull circuit featuring a complementary emitter-follower driver. Compared with the standard NTL circuit, this circuit offers a much better balance between the pull-up and pull-down delay, improved scalability, and superior load driving capability. Simulation results based on a 0.8-μm double-poly self-aligned complementary...
The authors present a single-poly bipolar technology using an advanced transistor with an LDD (lightly doped drain)-like self-aligned lateral profile. The device is isolated by a silicon-filled deep trench with a collector-to-collector breakdown voltage of 33 V, and the field oxide is provided by a low-temperature breakless process. The integrated process yields a structure with minimal topography,...
The author presents a detailed two-dimensional numerical simulation study on the performance degradation caused by the extrinsic base encroachment in advanced narrow-emitter bipolar circuits. It is shown that depending on the circuit families used, the extrinsic base encroachment results in distinct effects on the operation and performance of the circuits. The design considerations and scaling implications...
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