The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper considers aspects of low-frequency noise in the inversion-channel SOI nMOSFET and the buried-channel SOI pMOSFET. Analyses suggest that the inversion channel is strongly influenced by interface traps, which also weakly influence the buried-channel. It is demonstrated that such aspects are significant in the subthreshold bias range.
600 V-class superjunction (SJ)-MOSFETs were developed using our original high-resolution Scanning Spread Resistance Microscopy (SSRM) analysis technology [1] for optimization of trench filling process for the first time. The SSRM analysis is a powerful tool for the SJ structure design, because it can be achieved the measurement of two- dimensional (2D)-carrier profile and detect of minute voids. The...
Advantage of La2O3 over HfO2 MOSFET has been experimentally examined. Silicate reaction especially observed at La2O3/Si interface has been found to suppress the formation of SiO2 layer to realize direct contact, which is useful for further scaling in equivalent oxide thickness (EOT). Due to the lack of interfacial layer, La2O3 has showed relatively high interfacial state density, however, the effective...
This paper describes the temperature behavior of the phonon-limited electron mobility on the (111) and (001) Si surfaces of DG SOI MOSFET. We discuss the major difference of the phonon-limited electron mobility behavior on the (111) and (001) Si surfaces of DG SOI MOSFET at low temperature.
This work reports the influence of nitridation on structural and electrical properties of La 2 O 3 gate dielectric films. The issue of La 2 O 3 is EOT increase after high temperature post metarization annealing (PMA). To overcome this problem, we incorporated nitrogen in La 2 O 3 . The EOT increase on the TaN/LaON and W/LaON structure is reduced compared...
High-performance low operation power (LOP) transistors were developed for 45nm node universal applications. A high uniaxial strain and low resistance NiSi technique, enhanced by a slit under the slim and high Young's modulus (YM) offset spacer covered with dual stress liner (DSL), were used for electron and hole mobility enhancement and parasitic resistance (Rsd) reduction. The junction profile was...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.