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FinFET is a promising architecture for low-voltage/low-power applications at and beyond the 32 nm technology generation. VDD scalability of LSTP- and LOP-32 nm compatible FinFET SRAMs is investigated in the presence of fin line-edge roughness (LER). Several design options are compared, including transistor sizing, mobility changes as a result of crystal orientation, fin patterning and gate stack,...
The impact of fin line-edge roughness on threshold voltage and drive current of LSTP-32 nm Fin-FETs is estimated through TCAD simulations. A Monte Carlo approach highlights an increase in the average VT and a decrease in the average ION w.r.t. sensitivity analysis based predictions. Correlations of fin shape fluctuations to electrical performance are investigated. An equivalent fin width is calculated,...
Spacer-defined fin-patterning results in double/quadruple fin density and hence is attractive for high performance 32-nm CMOS applications. For the first time 55-nm gate-length FinFET SRAMs with resist- and spacer-defined fins are electrically compared. Due to short-range process variations, SRAM bit-cells with spacer-defined fins show approximately 2.5 times higher variability in static-noise-margin...
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