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In this paper we present a SPICE-compatible macro model based on three MOS transistors to describe split-gate non-volatile memory (NVM) cell characteristics for various sizes of the gap between the gates. The model has initially been developed based on simulated dc-IV-characteristics of reference cells (floating gate connected to control gate) and was verified later with measurements on reference...
For the scaling of embedded floating gate (FG) memories towards the 45nm CMOS generation and beyond, a reduction of the program and erase voltages is required. A solution is the use of high-k inter-poly dielectrics (IPD) to increase the coupling of the control gate (CG) to the FG. Compared with standard IPD materials like oxide-nitride-oxide (ONO), materials with higher k-values give a better coupling,...
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