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Once considered mature and commodity technology, CMOS Si technology keeps revamping itself as a collection of most innovative technologies known to humanity at this given time. Beyond conventional vanilla scale of SiON/Poly planar bulk Si technology, lab-level experiments constantly become manufacturing reality, such as high-k, metal gate, FDSOI, FinFET, and many exotic patterning technologies. This...
In this paper, we present a high performance planar 20nm CMOS bulk technology for low power mobile (LPM) computing applications featuring an advanced high-k metal gate (HKMG) process, strain engineering, 64nm metal pitch & ULK dielectrics. Compared with 28nm low power technology, it offers 0.55X density scaling and enables significant frequency improvement at lower standby power. Device drive...
We present an overview and electrical results for a novel deep trench decoupling capacitor. The process of this decoupling capacitor borrows from the regular embedded DRAM trench process, but with significant process simplification for decoupling use which provide reduced cost and reduced process cycle time. This capacitor can provide significant chip-level area savings, using only 1/8 silicon real...
Gate-induced-drain-leakage (GIDL) current in 45 nm state-of-the-art MOSFETs is characterized in detail. For the current technology node with a 1.2 V power-supply voltage, the GIDL current is found to increase in MOSFETs with higher channel-doping levels. In contrast to the classical GIDL current generated in the gate-to-drain overlap region, the observed GIDL current is generated by the tunneling...
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