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This paper first presents an analysis of the holding voltage of NMOS and PMOS SOI FinFETs in bipolar mode. Further, to make FinFETs an area-efficient technology option, geometrical parameters which are fixed by the current process will be scaled down. A TCAD simulation methodology is used to predict the robustness of scaled-down FinFETs.
The ESD performance of gated FinFET diodes and multi-gate NMOS devices in both active MOS-diode and parasitic-bipolar mode are investigated, highlighting the impact of strained SiN layers. Strain improves the ESD robustness up to 30% in multi-fin FinFETs. A different failure mechanism is discovered in strained NMOS FinFETs for the parasitic-bipolar mode.
A new design methodology for FinFET devices is presented which takes into account all complex dependencies on both layout and process parameters of the electrical ESD device parameters of FinFET gated diodes and NMOS FinFET devices in both parasitic bipolar and active MOS operation mode. This methodology allows optimization towards a given ESD target (area consumption, leakage current, parasitic capacitance,...
Electrostatic discharge performance of advanced FinFETs shows a delicate sensitivity to device layout and to processing parameters. Both N- and P-type MOS FinFET devices are characterized in bipolar operation mode as a function of layout parameters such as gate length and fin width. The impact of well implants, selective epitaxial growth, and strain is studied.
The electro-static discharge robustness of different elevated source drain architectures on a 90 nm CMOS technology is investigated. The study is performed on poly isolated diodes and grounded gate NMOS using transmission line pulse and human body model testing methods. It is found that an improvement up to 45% in ESD robustness can be obtained by the use of elevated source drain process option. Failure...
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