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A novel allocated-by-weight seed-based BIST (ASB) architecture has been proposed for combinational circuits to test. A test sequence of ASB is termed as seeded weighted Gray cyclic shift sequence (SW-GCSS), generated by Gray cyclic shift sequence (GCSS) and canonical seeds. GCSS, termed as the characteristic sequence is a single input change (SIC) sequence with transitions of its bits different from...
This paper presents an improved latched comparator which is suitable for high speed folding and interpolation ADC. The proposed comparator minimizes the kick back noise while regenerates the analog input signals. Injection reducing switch is introduced to suppress clock feedthrough and charge injection error. Transistors in common-gate arrangement are inserted to reduce kick back noise. Simulated...
This paper proposes a simplified algebraic model to present the complex configurations of single input change (SIC) circuits, and investigates the relationship between the SIC sequence and its generating circuit. Furthermore, several key properties of the studied sequence are provided and theoretically proved. Based on the above, we discover the commonness of different configurations of SIC circuits,...
A general approach is proposed for minimizing the chip area and minimizing the efficiency of the fully integrated CMOS continuous mode buck converters. It shows that most significant portion of the area is occupied by the passive component such as capacitors and inductors. Some design-oriented performance equations are proposed to show the key factors that determine the features of the converters...
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