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Stresses induced by the large volume of Cu in Through Silicon Vias (TSV) can result in global/local Cu extrusion which may affect reliability in 3D chip stacking technologies beyond the 28 nm node for high performance mobile devices. In this work, TSV structural factors that can influence extrusion post via filling are studied. In addition, the impact of the electroplating chemistry and annealing...
As semiconductor performance improvements through device scale-down becomes more difficult, 3D chip stacking technology with TSVs (Through Silicon Via) is becoming an increasingly attractive solution to achieve higher system performances by way of higher bandwidth, smaller form factor and lower power consumption. Such increase in performance using TSV aided 3D chip stacking technology applies not...
Electromigration in a hybrid interconnect which consists of copper metallization in via below, aluminum metallization in via above, and tungsten via in between has been investigated. Fatal failures are found to occur in copper segments of the hybrid structures we tested. Two distinct failure mechanisms in copper segments are observed. One type of failure occurs due to void nucleation at the interface...
We have developed tungsten nitride (W-Nitride) films grown by plasma enhanced chemical vapor deposition (PECVD) for barrier material applications in ultra large scale integration DRAM devices. As-deposited W-Nitride films show an amorphous structure, which transforms into crystalline, β-W2N and α-W phases upon annealing at 800°C. The resistivity of the as-deposited films grown at the NH3/WF6 gas flow...
CVD TiN using TiCl/sub 4/ and NH/sub 3/ chemistry has been implemented successfully in cylindrically shaped Ta/sub 2/O/sub 5/ storage capacitor as a barrier layer in poly-Si/TiN double upper electrode. Electrical characteristics of Ta/sub 2/O/sub 3/ capacitor with CVD TiN double electrode were superior to that with PVD TiN and it was attributed to nearly 100% conformality of CVD TiN. However, it was...
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