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For radiometric application in the frequency range around 325 GHz, two low noise amplifier millimeter-wave monolithic integrated circuits have been developed. They use metamorphic high electron mobility transistors with a gate-length of 35 nm. The first amplifier only uses transistors in common-source configuration, whereas the second only employs transistors in cascode configuration. Their simulated...
A static and a dynamic frequency divider based on enhancement and depletion 0.2 μm gate length AlGaAs/GaAs-HEMT (fT = 60 / 55 GHz) technology were designed and fabricated. High-speed operations up to 31 GHz and 39 GHz for the static and dynamic frequency divider, respectively, have been achieved. The single-ended input and differential output to ground simplify many applications. The power consumption...
An IC for 20 Gb/s clock recovery and data decision was realised using 0.3 ??m gate-length QW-HEMTs. A narrow-band regenerative frequency divider with on-chip resonator filters is used for the clock recovery. The parallel processing concept is accepted for the data decision. The complex IC was tested on wafer using 5 and 10-Gb/s input data. The desired 10-GHz clock signal and regenerated data signals...
A monolithically integrated clock recovery (CR) circuit making use of the phase-locked loop (PLL) circuit technique and enhancement/depletion AlGaAs/GaAs quantum well high electron mobility transistors (QW-HEMTs) with gate lengths of 0.3 μm has been realized. A novel preprocessing circuit was used. In the PLL a fully-balanced varactorless VCO has been introduced. The VCO has a centre oscillating frequency...
An integrated laser diode voltage driver (LDVD) making use of enhancement/depletion AlGaAs/GaAs quantum well high electron mobility transistors (QW-HEMTs) with a gate length of 0.3 μm has been developed. Its large signal bandwidth was 12 GHz. Eye diagrams of the output signal at bit rates up to 8 Gbit/s showed an opening like that of the input signal. Increasing the bit rate of the input signal by...
A high speed 2:1 multiplexer circuit in source coupled FET logic has been developed and fabricated using a recessed gate process for enhancement and depletion transistors with 0.3μm gate length. First results show a data rate of over 20 Gbit/s at 5 V supply voltage and 250 mW power consumption. The output voltage swing is adjustable between 0.3 V and 0.8 V for a 50 Ohm load. The out-put level can...
A 10 Gbit/s monolithic integrated optoelectronic receiver has been fabricated with a metal-semiconductor-metal (MSM) photodiode and enhancement/depletion 0.5 ??m recessed-gate AlGaAs/GaAs HEMTs. A -3dB bandwidth of 11.3 GHz has been achieved.
To increase performance of GaAs LSI digital circuits, a 0.5 μm recessed gate process has been developed and utilized for an 8??8-b parallel multiplier. The chip contains about 3000 heterostructure field effect transistors and has a power consumption of 1.5 W. The best results of the maximum multiplication time measured were below 2.5 nsec.
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