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This paper presents, for the first time, a novel silicon damascene like via-in-trench (ViT) interconnect for panel-scale package redistribution layer (RDL) configuration. The panel scale damascene RDL in this paper comprises of ultra-fine copper embedded trenches and microvias with diameter equal to the width of trenches using a 5 µm thick dry film photosensitive dielectric. A 140 µm thick glass substrate...
This paper describes for the first time an innovative approach to improve re-distribution layer (RDL) yields in advanced semi-additive processes (SAP). An atmospheric pressure ozone based treatment is proposed as an alternative to oxygen plasma treatment. The ozone treatment process is scalable, being appropriate for process wafers up to large panels, and is suited for small feature sizes down to...
This paper presents the latest advances in extending semiadditive process (SAP) methods to 2–5 $\mu \text{m}$ lines and spaces, achieved using dry film photoresists on thin glass substrates, toward meeting the routing requirements for 20-$\mu \text{m}$ bump pitch interposers. High-density chip-to-chip interconnections on 2.5-D interposers are a key enabler to meet the high logic to memory bandwidth...
This paper discusses the effect of process induced variations in copper transmission lines on their electrical performance up to 110 GHz, fabricated by semi-additive processes (SAP) for redistribution layers (RDL). The motivation of this research is to quantify the effect of the process variations in RDL traces by SAP, thus enabling electrical designers to reduce design iterations to achieve precise...
This paper describes the improvement of advanced semi-additive processes (SAP) to demonstrate 1.5-5 µm lines and spaces with 4-5 µm diameter photo-vias for multiple re-distribution layers (RDL) at 20 µm bump pitch on glass interposers. High performance computing systems for networking and graphics are driving ultra-high bandwidth interconnections between logic and memory devices. This signal bandwidth...
Interposer technology is becoming important to interconnect ultra-high performance ICs with ultra-high density I/Os. Silicon interposers fabricated by back-end of line (BEOL) wafer processes address these wiring density requirements, but are limited by their high cost and by their high electrical losses. Organic interposers have limitations too. Their limitations are due to their poor dimensional...
This paper presents the first demonstration of polycrystalline silicon interposers with fine pitch through package vias (TPV), with less than 5μm RDL lithography at 50μm pitch copper microbump assembly. Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wiring offer compelling benefits for 2.5D and 3D system integration; however, they are limited by high cost and high...
First principles calculations have been performed to investigate the structural, thermodynamic and electronic properties of four common intermetallic compounds (IMCs) formed at the solder joints of electronic packages, namely, Cu6Sn5, Cu3Sn, Ni3Sn4 and Ag3Sn. The theoretical heat of formation of Cu6Sn5 is close to that of Cu3Sn, both of them are overestimated relative to the experimental results....
Electromigration resistance of Al could be improved through adding a small amount of Cu elements. In this paper, Al31Cu supercell was constructed to calculate the effects of the solute elements on the properties of face central cubic (FCC) Al, including the diffusion activation energy, electronic structure etc, to explain why Cu can suppress the EM process occurred in pure Al interconnect, by employing...
A 40 Gb/s low-power analog equalizer has been realized in 0.13 mum CMOS technology. To achieve a peaking gain of 10 dB at 20 GHz and low power dissipation, an inductive feedback stage is proposed. This inductive feedback stage consumes 3.6 mW from a 1.2 V supply and the whole equalizer consumes 14.4 mW. The chip occupies 0.57 times 0.44 mm2. For a 40 Gb/s PRBS of 27-1, the measured BER is less than...
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