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In-field test of electronic devices is becoming increasingly important due to the wide adoption of electronic systems in safety-critical applications. Hence, it is crucial to devise and deploy effective solutions supporting the test during the operational phase of all the components of an electronic system, including the memory modules embedded in a SoC. Some key aspects include the possible reuse...
Testing embedded microprocessors at mission time is nowadays a requirement in many SoC applications. In this paper, we introduce a methodology where the detection of operational faults is performed while the normal operations are temporarily suspended, by means of an ad-hoc HW module connected to the address, data and control buses of the microprocessor. This module behaves as a peripheral towards...
In this paper, we propose an innovative emulation-based framework for the generation of test programs oriented to SMT microprocessor validation. The two major characteristics of the proposed framework are an effective method to gather information about the processor internal status via its emulation, and an efficient algorithm which exploits these pieces of information for a generation process which...
This paper describes an agent oriented framework supporting bio-inspired mechanisms which takes profit of the intrinsic hardware parallelism of the pervasive platform developed within the Perplexus IST European project. The proposed framework is a flexible and modular means to describe and simulate complex phenomena such as biologically plausible neural networks or culture dissemination. Associated...
The ubichip is a bio-inspired reconfigurable circuit developed in the framework of the European project Perplexus. The ubichip offers special reconfigurability capabilities, being the dynamic routing one of them. This paper describes how to exploit the dynamic routing capabilities of the ubichip in order to implement synaptogenetic neural networks. We present two techniques for dynamically generating...
A practical system approach for time-multiplexing cellular neural network (CNN) implementations suitable for processing large and complex images using small CNN arrays is presented. For real size applications, due to hardware limitations, it is impossible to have a one-on-one mapping between the CNN hardware cells and all the pixels in the image involved. This paper presents a practical solution by...
The described microprocessor is a micropower multitask machine with a hardware scheduler. The task switching is performed at the instruction level. The programmer may choose a task configuration, i.e. one to four pseudo-parallel tasks depending on the application. To replace a software scheduler by a hardware scheduler allows to reduce the power consumption.
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