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Ion beam milling is successfully implemented for smoothing roughness of the fin sidewalls for the FinFETs with poly-crystalline TiN metal gate (MG). The Vt variability is improved significantly by smoothing the fin roughness without degradation of the carrier mobility. The suppressed Vt variability is interpreted as improved uniformity in the grain orientation of TiN which causes work function variation...
This paper presents a low-power and low-voltage 64-kb 8T three-port image memory using a 28-nm FD-SOI process technology. Our proposed SRAM accommodates eight-transistor bitcells comprising one-write/two-read ports and a majority logic circuit to save active energy. The test chip can operate at a supply voltage of 0.46 V and an access time of 140 ns. The energy minimum point is a supply voltage of...
Performance of a double-gate (DG) FinFET in the cryogenic environment is discussed based on measurements and simulation. It was found that the DG FinFET has an excellent immunity to the kink effect in the cryogenic environment. Our physics-based compact model reproduced the measured I–V characteristics. The successful demonstration of an opamp consisting of the DG FinFETs at 4.2 K is also presented.
As the scaling of conventional MOSFETs approaches its technological limit, the double-gate (DG) MOSFETs have emerged as an important candidate for the next generation device. As a novel device with an additional fourth terminal, the DG devices have a potential to evolve not only in the More-Moore way, i.e. short channel effects and variation prevention, but also in the More-than-Moore direction, i...
An adaptive-threshold-voltage differential pair and a low-voltage source follower using independent-double-gate-(IDG-) FinFETs are proposed for a low-voltage operational amplifier (op amp). These circuits were implemented by our FinFET technology that enables co-integration of connected-DG- (CDG-) and IDG-FinFETs. The proposed components enable a two-stage op amp to accept the input below the nominal...
This paper presents a method to salvage malfunctioned bits in a FinFET SRAM array caused by random threshold voltage (Vt) variation. The Vt of pass gates (PGs) is gradually lowered during the read process from the initial high value until the stored data is detected by the sense amplifier. As a result, the best Vt is automatically chosen for each cell and malfunctioned bits of both those too fast...
The area penalty, operation stability, and operation speed of the 20-nm-ZG FinFET SRAM were compared to those of the 20-nm-ZG bulk-planar SRAM. The FinFET SRAM with beta-ratio of 1 is expected to realize not only 7% less area penalty, but also the same or superior operational stability to that of the bulk-planar SRAM with beta-ratio of 2 because of less variability of the device performance. Also,...
A FinFET compact model, which provides physical representation of measurement data, was developed and was successfully applied to the characterization of sate-of-the-art metal-gate (MG) FinFETs. By combining the transistor size measurement and the model parameter calibration, the Vth variation of the MG FinFETs was analyzed into structure-based (TSi, LG) and material-based (gate work-function) variations...
We demonstrate midgap and band-edge effective workfunctions (EWFs) control with simple metal gate process scheme (singlemetalgate/singlegatedielectric), using impurity-segregated NiSi2/SiON structure for embedded memory application. The application of midgap and band-edge EWF enables us to lower power consumption in SRAM and logic devices by 30% and 15% compared to poly-Si devices, respectively,...
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