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The significance of impurity profile design for source/drain extension (SDE) is widely recognized for deeply scaled MOSFET. In this paper, novel SDE formation scheme in planar pMOSFET is discussed using plasma doping (PD) and laser spike annealing (LSA), comparing with conventional Ion Implantation (II) technique. It is found that the combination of PD and high-temperature LSA can realize the abrupt...
We have presented the high performance pMOSFET with embedded SiGe (eSiGe) technique which is applicable to 32 nm node ground rule (dense gate space). In general, close eSiGe S/D structure to the channel improves pMOSFET performance because of higher strain in the channel. However, we found the relation between boron diffusion modulation in SiGe region and short channel effect (SCE) in the context...
Recently, we reported significantly improved spatial resolution in scanning spreading resistance microscopy (SSRM) by measuring in a vacuum. In this paper, we demonstrate the 1-nm spatial resolution of SSRM in carrier profiling by comparing with the 3-D device simulation. The simulation results show that the accuracy of ultrashallow-junction delineation depends on the effective radius of the probe...
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