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We have developed a device integration scheme for embedded silicon carbon (Si:C) SD structures induced by the solid phase epitaxy (SPE) technique. Our integration scheme comprises a combination of three key processes: carbon ion implantation (I/I) with Ge pre-amorphization implantation (PAI), sRTA and LSA. The guideline of our scheme is as follows. First, carbon I/I with Ge PAI plays large roll in...
This paper reviews main technologies of embedded silicon germanium (eSiGe) for 45 nm node and beyond .There are three key techniques and an item to be considered carefully as follows. The first technique is a low temperature of epitaxial growth at 550degC to suppress stacking faults in eSiGe layer. The second one is a controlling of recess shape for eSiGe. Sigma(Sigma)-shaped recess is applied, because...
Direct comparison between competitive process flows showed that the eSiGe-S/D-last flow is the most promising CMOS integration process for manufacturing 45-nm technology node and beyond because it has good extensibility with various performance boosters, has fewer process steps and suppresses electrical fluctuations. The eSiGe-S/D-last (after offset spacer + I.I.) flow creates a sufficient process...
We developed novel junction profile engineering that uses a newly developed multiple laser spike annealing scheme and applied it to 45-nm node high performance and low leakage CMOS technology. This novel junction profile engineering is effective for the performance improvement of CMOS devices with embedded SiGe in the PMOS regions. Reduction of the source-drain parasitic resistance and the junction...
The impact of defects on the short channel effects (SCE) and the drivability of a pMOSFET with a SiGe source/drain is described, and useful methods to reduce defect formation are suggested. The influence of defects on device performance is found to become more severe as recess depth increases and/or channel length decreases. By optimizing the epitaxial process, including an in-situ precleaning step,...
Aggressively scaled 30nm gate CMOSFETs for 45nm node is reported. We successfully improved a higher drive current with keeping the short channel effect by Sigma shaped SiGe-source/drain (Sigma SiGe) structure using compressive-stressed liner. In addition, we developed novel stack-SIN gate dielectrics by using bis-tertiarybutylamino-silane (BTBAS)/NH3. Novel stack-SIN gate dielectrics show higher immunity...
Aggressively scaled 30 nm gate CMOSFETs for 45 nm node is reported. We successfully improved the short channel effect with keeping a high drive current by Sigma shaped SiGe-source/drain (SiGe-SD) structure. Both hole mobility and source/drain extension (SDE) resistance in pMOSFET are improved by combination of optimized Sigma shaped SiGe-SD and slit-embedded B-doped SiGe-SDE. Electron and hole mobility...
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