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Cu pumping is a potential reliability issue for through silicon via (TSV) based 2.5D and 3D integration, due to the CTE mismatch between silicon and copper. In this paper, we report the reliability assessment of Cu pumping treated at different annealing conditions. Cu pumping is simulated by finite element method to compare the effect of the overburden layer. The pumping of TSVs having a diameter...
The main challenge of Low Temperature (LT) Solid Phase Epitaxy (SPE) is the dopant deactivation during post activation anneal. For the first time, we demonstrate that, for LT-SPE activated Boron (B) on thin SOI substrates, B deactivation can be well controlled during post anneal at 400 °C–600 °C. This is achieved by locating the preamorphization induced end of range defects close to the Buried OXide...
For the first time, low temperature (LT) anneal at 625°C has been demonstrated for dopants activation enabling similar ION/IOFF trade-off as standard spike anneal (>1000°C), down to 30nm gate length (LG) for both n&p FETs. Similar short channel effect control has been achieved in LT n&p FETs as its high temperture (HT) counterparts. Influence of dopant implant tilt on LT device performance...
In this paper, we demonstrate low junction leakage for devices fabricated at low temperature (≤ 650°C). This is explained by the reduced channel thickness of our device (6 nm). We show this through both experimental data and KMC simulations that enable to understand the origin of the leakage reduction.
Electromagnetic (EM) modeling and simulation techniques for passive linear systems as in 3D ICs and SIPs are presented. On TSVs' we present high throughput analytical 2D admittance (CG) and impedance (RL) models, with consideration of MOS effect in silicon. These 2D models are computationally useful for parasitic estimates, while the simulation of critical subsystems requires 3D accurate models. We...
We report a detailed experimental and theoretical investigation on the photocurrent characteristics of nanocrystalline Si thin films, with the emphasis on the effect of Si dot size distribution. Broader photocurrent response has been observed in Si quantum dots with larger size dispersion due to the improvement of light harvest. As a result of tunneling loss in the expanded energy distribution, we...
In this paper, we analyze the performance impact of different number of Through Silicon Vias (TSVs) in 3D Network-on-Chip (NoC). The adoption of a 3D NoC design depends on the performance and manufacturing cost of the chip. Therefore, a study of the placement of the TSV, that connects different layers of a 3D chip, is crucial. A 64-core 3D NoC is modeled based on state-of-the-art 2D chips. We discuss...
22nm node Si SOI Coplanar “N Channel Vertical Dual Carrier Field Effect Transistors” (VDCFET) and its SOC with effective channel length less than 10nm for communication applications are presented.
We present the shortest and narrowest high-κ/metal gate n- and pFETs on compressively strained enriched SiGe On Insulator (c-SGOI) reported to date (LG=20nm; W=30nm; TSiGe=15nm). The range of active area widths in this work allows observing the transition from biaxial to uniaxial stress due to lateral elastic strain relaxation, and its benefit down to 20nm gate length on hole mobility and pFET performance...
Hydrogen solubility of amorphous Pd 1-x Si x (x = 0.15, 0.175, 0.2) alloys in the form of ribbon, which were prepared with a single-roller melt spinning technique, was measured by a pressure-variable method at elevated temperatures up to 200°C. It was found that the hydrogen solubility in the amorphous alloys, strongly depending on the Si content, decreased with an increase...
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