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The thermal stability of CoSi2 layers on P-doped polycrystalline Si was investigated. It was observed that the additional Ge+ implant is performed prior to Co sputtering can suppress the CoSi2 agglomeration behavior. The samples with Ge+ implant at 50KeV implanted energy and more than or equal to the dose of 2E15 ions/cm2 show that the agglomeration of CoSi2 film is completely suppressed during high...
This investigation employs an optimized method to alleviate defects occurring at BF2+ implanted source/drain areas, some white spots defects found at scribes lines after BPSG (boron and phosphorus doped silicon glass) anneal. The results of physical failure analysis indicate the white spot defects are relative to outgassed fluorine that can't be released out during BPSG thermal annealing. Various...
For Solid-State Drive (SSD) applications cycling endurance of NAND flash is a critical challenge. In this work the endurance reliability of BE-SONOS NAND is thoroughly examined. Using dual CV/IV tests the impact of interface state (Dit) generation/annealing and real charge trapping (Q) on the endurance degradation has been clearly identified. For BE-SONOS with pure thermal oxide O1, the endurance...
The present study investigates the charge trapping characteristics of Si-rich nitride thin films in detail by using the gate-sensing and channel-sensing (GSCS) method. Analytical results indicate that thicker (>7 nm) nitride thin films are fully-capturing; the trapped electrons are distributed in the center of the nitride, and the charge centroid is independent of the N/Si ratio. However, thinner...
A double-layer TFT NAND-type flash memory is demonstrated, ushering into the era of three-dimensional (3D) flash memory. A TFT device using bandgap engineered SONOS (BE-SONOS) (Lue et al., 2005, Lai et al., 2006) with fully-depleted (FD) poly silicon (60 nm) channel and tri-gate P+-poly gate is integrated into a NAND array. Small devices (L/W=0.2/0.09 mum) with excellent performance and reliability...
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