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This paper presents the methods of eliminating the plasma-induced Si substrate damage in periphery regions, resulting from high aspect ratio etching process for 3D NAND fabrication. The impact of Si substrate damage is verified by the low and high bias power experiments. The result indicates more Si damage is present with high energy bombardment; therefore, high bias power is recommended to be inhibited...
We present several efforts for arcing reduction during high aspect ratio etching. Strategies including pulsing etching adjustments, ex situ multi-cyclic etch approach, flush step incorporation, E-chuck voltage operation, cap material, etc. are explored. The details are discussed in the paper.
We present several efforts for arcing reduction during high aspect ratio etching. Strategies including pulsing etching adjustments, ex situ multi-cyclic etch approach, flush step incorporation, E-chuck voltage operation, cap material, etc. are explored. The details are discussed in the paper.
Pattern dependent charging effect is explored in this study. Due to increased film thickness in 3D NAND structure, a derivative problem-the plasma-induced charging damage is enhanced during high aspect ratio (HAR) etching. In this paper, several effective methods are demonstrated to alleviate the impact of profile distortion due to charging effect while etching high aspect ratio (>14) trenches.
NF3/NH3 remote plasmas are used in oxide etch back process prior to the salicide process of word lines (WL) owing to high etch selectivity of silicon oxide over polysilicon. The etch saturation behavior which performs etch stop with a certain period of process time is one of the interesting characteristics during oxide etch process by employing NF3/NH3 remote plasmas. In this study, it is found that...
This paper presents a case study on a process excursion where a subtle defect spray with twelve pairs of defects aggregated flow pattern on the front side of the wafer. The defect of interest is molten tungsten (W) balls which are generated in a dielectric etch chamber caused by plasma arcing between one part of the etch chamber and the dissimilar W film remaining on the wafer bevel. Observations...
Down-flow plasma etching is mentioned instead of high-density capacitively coupled plasma (CCP) etching to prevent the control gate (CG) against physical damage during the intra-level dielectric (ILD) etch back, which is the process prior to form cobalt silicide word lines. However, owning to lack of ion bombardment, it is hard to achieve good etch uniformity. This paper presents the design of experiments...
The TiN was conventionally used as barrier layers for both tungsten plug and AlCu metal lines. This paper reveals a novel back end of line (BEOL) self-aligned double patterning (SADP) technology, which applied TiN as a spacer material. The relative processes are introduced and discussed in detail. The new SADP approach was further applied for Cu damascene structure constructions in the advanced non-volatile...
This paper identifies post etch killer defects, e.g., core bridging, small particle and tiny bridging, and investigates the possible solutions in a SADP module. Among the killer defect adders, core bridging and small particle are commonly observed after the oxide core removal by BOE. Core bridging adder is a carbon-containing polymeric by-product during nitride spacer open; by introducing additional...
This paper describes the advanced control technology of critical dimension uniformity (CDU) by flash gate stack etch process. We have investigated the effective way of utilizing Tri-layer approach, which not only reduces the influence of topology step-height but also improves the range of ECD within die from 17.6nm to 4.9nm. Moreover, the influence of Etcher design on ECD variation becomes larger...
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