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This paper presents a vertical gate-all-around nanowire FET (VFET) architecture targeting 5nm and beyond technologies, and a new standard-cell construct for digital flow implementation. VFET technology circuits and parasitics for processes and design features aligned with 5nm CMOS are systematically assessed for the first time. Self-aligned quadruple pattering (SAQP) is implemented to achieve required...
Design-Technology co-optimization becomes a key knob to enable CMOS scaling. In this work we evaluate the technology options including lithography options as well as device options that are considered to enable N10 scaling by exploring their impact on representative designs such as standard cells, SRAM and analog contexts. This paper illustrates that the design angle needs to be considered early in...
Smart Mobile SoCs combine the need for speed and for power efficiency. For the 7nm node, high-mobility materials (SiGe, Ge, and IIIV) are candidates to replace Si channels and continue speed improvement, but are more prone to leakage currents impacting active leakage power. Transport and voltages at scaled dimensions could also influence the benefit of higher mobility. We evaluate these aspects for...
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