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This paper presents a low power FFT accelerator using a Radix-2 algorithm with an 8-parallel multi-path delay commutator. Hardware accelerators can achieve better performance and throughput compared to software FFT routines. Thus, FFT accelerators are used in many DSP processors. In this paper, a Radix-2 Multipath Delay Commutator (R2MDC) FFT accelerator is designed with 8-parallel processing of the...
In this paper, a high throughput and low power architecture for 256-point FFT processor is proposed which is suitable for both high performance and low power applications. The proposed architecture is based on Radix-4 algorithm. We choose pipelined Multi-path Delay Commutators (MDC) for our design. Two separate datapaths are used in this architecture so that it can process eight inputs in parallel...
In this paper, a hardware efficient convolution implementation is proposed which is based on the Hirschman Optimal Transform (HOT). Previously, it has been shown theoretically that convolution based on HOT has major cost advantage over FFT based convolution, since, a K2 point HOT is based on a K-point DFT. However, due to the complexity of the HOT convolution, it was not easily realizable on hardware...
In this paper, we propose a hardware architecture to compute the Hirschman Optimal Transform (HOT). The HOT promises faster computation than the FFT with reduced area, yet can be used in similar ways. In fact, the HOT can potentially yield faster FIR convolution and superior spectral analysis methods. An N=K2 point HOT is composed of K, K-point DFTs. For our work, these K-point DFTs are computed using...
The increasing complexity of applications with a decreasing time-to-market requirement has created a strong interest in both high-performance and flexible embedded processors with a strong consideration for battery life. Low-power optimizations are therefore often applied toward the development of Application-Specific Instruction-Set Processors (ASIPs). In this paper ASIP accelerators for a typical...
In this work we present a 3-dimensional (3-D) model for the simulation of Polymer Electrolyte Fuel Cell (PEFC). The model is implemented in our in-house semiconductor and circuit simulator developed at Florida State University, RandFlux [1]. The transport equations are written in a form similar to the transport equations in semiconductor devices, which makes our model easy to be numerically implemented...
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