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In this paper, a hardware efficient convolution implementation is proposed which is based on the Hirschman Optimal Transform (HOT). Previously, it has been shown theoretically that convolution based on HOT has major cost advantage over FFT based convolution, since, a K2 point HOT is based on a K-point DFT. However, due to the complexity of the HOT convolution, it was not easily realizable on hardware...
In this paper, we propose a hardware architecture to compute the Hirschman Optimal Transform (HOT). The HOT promises faster computation than the FFT with reduced area, yet can be used in similar ways. In fact, the HOT can potentially yield faster FIR convolution and superior spectral analysis methods. An N=K2 point HOT is composed of K, K-point DFTs. For our work, these K-point DFTs are computed using...
Distributed arithmetic (DA) is performed to design bit-level architectures for vector-vector multiplication with a direct application for the implementation of convolution, which is necessary for digital filters. In this work, a DA based FIR adaptive filter implementation scheme is proposed. Different from existing DA schemes, our proposed scheme uses coefficients as addresses to access a series of...
In this work we propose a graph based minimum adder depth algorithm for the multiple constant multiplication (MCM) problem. Hence, all multiplier coefficients are here guaranteed to be realized at the theoretically lowest depth possible. The motivation for low adder depth is that this has been shown to be a main factor for the power consumption. An FIR filter is implemented using different MCM algorithms,...
Fast multiplication can be achieved by using canonical signed digit (CSD) to speed-up computations. Conversion to CSD is needed when the multiplier is not known a priori. In this work, a novel approach for converting an unsigned binary number or two's complement number to its CSD form from least significant bit to most significant bit, (right-to-left), is presented. Comparison shows that our algorithm...
Distributed arithmetic (DA) is performed to design bit-level architectures for vector–vector multiplication with a direct application for the implementation of convolution, which is necessary for digital filters. In this brief, two novel DA-based implementation schemes are proposed for adaptive finite-impulse response filters. Different from conventional DA techniques, our proposed schemes use coefficients...
In this work, the trade-offs in FIR filter design are studied. This includes the adder depth for the constant filter coefficients, the number of adders, and the number of delay elements, i.e., the filter order. It is shown that the proposed design algorithm can be used to decrease both the overall arithmetic complexity and the adder depth, possibly with a small penalty in delay elements. This is achieved...
In this work we consider three different techniques for avoiding sign-extension in constant multiplication based on shifts, additions, and subtraction. Especially, we consider the multiple constant multiplication (MCM) problem arising in transposed direct form FIR filters. The main advantage of avoiding sign-extension is the reduced load of the sign-bits. Furthermore, the complexity is slightly reduced...
Multiplication is performed frequently when implementing finite impulse response (FIR) filters. In most cases, rounded products are necessary to circumvent the growth of word length in order to reduce the area requirement and power dissipation and to speed up the circuit. However, due to rounding or truncating, errors are caused. In addition, in the FIR filter implementation, because of internal truncation,...
Implementation of digital signal processing (DSP) algorithms in hardware, such as field programmable gate arrays (FPGAs), requires a large number of multiplications. In this paper, we introduce a novel multiplier structure that converts from 2's complement to Canonical Signed Digit (CSD) representation in real time. The proposed algorithm increases the number of zero partial products (which can be...
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