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This paper presents a dual-mode delta-sigma modulator. The modulator can be configured for two structures, 3rd-order 4-bit in low-frequency high-resolution applications, and 2nd-order 4-bit in high-frequency low-resolution applications. Most of the circuit parts including the capacitors and switches are shared in both modes. An efficient OTA and comparators with Input Offset Calibration technique...
This paper describes design techniques of enabling energy-efficient 3-tap decision feedback equalizer (DFE) to operate adaptively at 40Gb/s in 65nm CMOS technology. First, we propose a closed-loop architecture utilizing three techniques to achieve the 1st tap stage design, namely a merged latch and summer, reduced latch gain, and a dynamic latch design. Then, we suggest to merge the feedback MUX with...
This paper describes design techniques of enabling energy-efficient 3-tap decision feedback equalizer (DFE) to operate at 40Gb/s in 65nm CMOS technology. First, we propose a closed-loop architecture utilizing three techniques to achieve the 1st tap stage design, namely a merged latch and summer, reduced latch gain, and a dynamic latch design. Then, we suggest to merge the feedback MUX with the tap...
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