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The dependence of the MOSFET threshold voltage variability on device geometry (width (W) and length (L)) has been studied from experimental data. Our results evidence, in agreement with other works, deviations from the Pelgrom's rule, especially in smaller technologies. TCAD simulations were also performed which further support the experimental data and provide physical information regarding the origin...
DC characteristics of AlGaN/GaN on Si MOS-HEMTs are measured and numerically simulated, with substrate temperature up to 140°C, varying the gate width and gate length. Different gate recess depths are simulated in ATLAS in order to further investigate and optimize the device performance. Thermal boundary conditions and device thermal resistance are included in the structure for accurate simulation...
Interface traps can be a source of variability in MOSFETs, leading to statistically distributed electrical characteristics of devices. This work discusses, from 3D TCAD simulations, the effect of the spatial distribution of interface traps on the variability of the threshold voltage and the on-current of MOSFETs. The results suggest that threshold voltage is mainly influenced by the trap distribution...
One of the most promising emerging memory technologies is the Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM), due to its high speed, high endurance, low area, low power consumption, and good scaling capability. In this paper, we estimate the STT-MRAM cell reliability under fabrication- and aging-induced process variability, by evaluating its failure probability. We analyze the effect...
A new method for the analysis of multilevel Random Telegraph Noise (RTN) signals has been recently presented, which can also be applied in the case of large background noise. In this work, the method is extended to evaluate the RTN-related variation of the device drain current. The RTN parameters obtained from experimental traces are used to simulate the impact of RTN in the drain current of pMOS...
Interface traps can introduce random variations in the drain current of MOSFETs, becoming a source of device variability. In this work, 2D and 3D TCAD simulations of devices with channel length in the decananometer range are carried out to analyze the impact of their spatial distribution on the drift of the threshold voltage. 2D simulations show that traps located close to the center of the channel...
Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs) and are susceptible to undergo defects at different stages: during their own fabrication, the bonding stage or during their life time. Typical defects are microvoids, underfilling, misalignement, pinholes in the oxide or misalignments during bonding in such a way that resistive opens become a frequent...
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