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A high speed, low delay/log(ΔVin) dynamic comparator using negative resistance combined with input differential pair is proposed and designed in TSMC 90nm CMOS process technology. The delay/log(ΔVin) of the comparator is 22ps/dec and consumes 213μW at 3GHz clock rate and 1.2V supply. The standard deviation of the comparator input refer offset is 25mV.
With the use of non-tree topology in signal nets, the delay issue in non-tree topologies has become an important problem. In this paper, based on the transformation-based timing analysis for a non-tree interconnection, an iterative wire-sizing approach is proposed to assign feasible widths onto the wire segments to minimize the timing delay in the critical path for a non-tree interconnection under...
In this paper, based on the equivalent circuit of on-track or off-track redundant via insertion and the timing delay of each net in as the timing constraint, an enhanced timing-constrained two-phase insertion approach for yield optimization is proposed to insert on-track and off-track redundant vias. For the Poisson yield model in redundant via insertion, the experimental results show that our proposed...
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