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The optical and electrical properties of a new type photonic-plasmonic nanostructure on the back contact of solar cells were investigated numerically through the three-dimensional (3D) finite-difference time-domain (FDTD) method and the poisson and drift-diffusion (DDCC) solver. The focusing effect and the Fabry-Perot resonances are identified as the main mechanisms for the enhancement of the optical...
This paper aims to investigate the bankrupcy decisions in the context of a supply chain with many upstream firms and one downstream firm, who face price uncertainty evovling as a stochastic process. The optimal bankrupcy thresholds are analytically derived for both upstream and downstream firms in this framework. Following the optimal exit strategies proposed in this paper, all firms would collaboratively...
Service-Oriented Architecture (SOA) is intended for the integration of heterogeneous applications. Complex business processes can be composed by a group of concrete Web services using WS-BPEL (Business Process Execution Language), and these Web services may be designed by the enterprise itself or provided by some third-party services providers. Today there are many WS-BPEL engines available that support...
Error correction code (ECC) and built-in self-repair (BISR) schemes have been wildly used for improving the yield and reliability of memories. Many built-in redundancy-analysis (BIRA) algorithms and ECC schemes have been reported before. However, most of them focus on either BIRA algorithms or ECC schemes. In this paper, we propose an ECC-Enhanced Memory Repair (EEMR) scheme for yield improvement...
Three-dimensional (3D) integration has recently become a popular technology for integrated circuits (IC). 3D IC with the passive silicon interposer is currently the main trend in the industry, especially for processor-memory integration. Evaluating the economic efficiency of test operations in the interposer-based 3D IC thus is important. We propose a cost model for the Die-to-Wafer (D2W) and Die-to-Die...
Built-in self-test (BIST) is one of the most widely used design-for-testability (DFT) techniques, particularly for embedded random access memory (RAM). To ease the test and diagnosis flow, we have previously developed a synthesis compiler, called BRAINS which stands for BIST for RAM in Seconds. It possesses many nice features, such as accessibility, scalability, programmability, and flexibility, thereby...
Pre-bond test is preferred for a three-dimensional integrated circuit (3D IC), since it reduces stacking yield loss and thus saves cost. In this paper, we present two schemes for testing through-silicon vias (TSVs) by performing on-chip screening before wafer thinning and bonding. The first scheme is for blind TSVs, which have one end floating, using a charge-sharing technique commonly seen in DRAM...
We present a novel testing scheme for TSVs in a 3D IC by performing on-chip TSV monitoring before bonding, using a sense amplification technique that is commonly seen on a DRAM. By virtue of the inherent capacitive characteristics, we can detect the faulty TSVs with little area overhead for the circuit under test.
HCV (Hepatitis C virus) that the NS3 protease and NS5B RNA-dependent RNA polymerase (RbRp) which the enzymes for virtual replication. HCV plays an important role that to cause the chronic and liver diseases. The computer aided drug design (CADD) that is the new method to design the new molecules as like the drugs from the potent compounds. We took the program of Discovery Studio 2.0 and the scoring...
As fabrication technology progresses, several new challenges follow. Among them, the most noticeable two are process variations and leakage current of the circuit. To tackle these two problems, an effective way is to use body biasing technique. In substance, using RBB technique can minimize leakage current but increase the delay of a gate. FBB technique decreases the delay but increases leakage current...
Dynamic power noises may not only degrade the circuit performance but also reduce the noise margin which may result in the functional errors in integrated circuit. Decoupling capacitor (decap) allocation is one of the most effective way in reducing serious dynamic power noises (hotspots). To allocate decap before placement, we observed that not only locations but also rising time of functional cells...
Microsomal prostablandin E synthase-1 (mPGES-1) has been recently investigated to be a novel and promising target for inflammation-related diseases. The quantitative structure-activity relationship (QSAR) study was used to explore the critical pharmacophore features of mPGES-1 by using a set of 35 azaphenanthrenone derivatives. Twenty four selected pharmacophore models derived from 240 hypotheses...
In modern sequential VLSI designs, clock tree plays an important role in synchronizing different components in a chip. To reduce peak current and power/ground noises caused by clock network, assigning different signal polarities to clock buffers is proposed in previous work. Although peak current and power/ground noises are minimized by signal polarities assignment, an assignment without timing information...
To simulate ventricular cardiac action potentials used Luo-Rudy phase I cell model with hybrid method, the computation time can be 100 times faster than RK4 (fixed step 0.01). However, the hybrid method of time step 0.8-2.0 causes the irregular S:R ratio by Wenckebach periodicity as stimulation 30 beats; other hybrid methods can adequately simulate cardiac physiology phenomena and prevent from phantom...
A study on the reverse current phenomenon in synchronous rectifiers is presented in this paper. For loss reduction, the synchronous rectifiers composed of MOSFETs have recently been employed to replace the conventional rectifiers with diodes in low voltage and high current applications. Because the MOSFETs in the synchronous rectifiers are used as bidirectional switches, reverse current flow will...
As feature size keeps shrinking, how to maintain the reliability becomes an important issue in IC production, especially for high density memory circuits. Error detection and correction (EDAC) schemes have been widely used for memory circuits for this purpose, but ordinary EDAC schemes are not suitable for memories with long codewords. The demand for low-power memory is increasing due to the growth...
In deep sub-micron technology, the crosstalk effect between adjacent wires has become an important issue, especially between long on-chip buses. This effect leads to the increase in delay, in power consumption, and in worst case, to incorrect result. In this paper, we propose a de-assembler/assembler structure to eliminate undesirable crosstalk effect on bus transmission. By taking advantage of the...
To meet the requirements of smaller devices while still maintaining high performance, it is necessary to form shallow source/drain extensions with high activation. For 65 nm devices, reducing the "peak width" of spike annealing will enhance device performance. Two RTP tools were compared by 65 nm device performance with different residence times (1.4 s and 1.85 s). Spike anneal thermal profile...
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