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We present an implementation of an algorithm for constructing provably fast circuits for a class of Boolean functions with input signals that have individual starting times. We show how to adapt this algorithm to logic optimization for timing correction at late stages of VLSI physical design and report experimental results on recent industrial chips. By restructuring long critical paths, our code...
We introduce in this paper a new problem of ECO timing optimization using spare-cell rewiring and present the first work for this problem. Spare-cell rewiring is a popular technique for incremental timing optimization and/or functional change after the placement stage. The spare-cell rewiring problem is very challenging because of its dynamic wiring cost nature for selecting a spare cell, while the...
This paper studies microprocessor floorplanning considering thermal and throughput optimization. We first develop a stochastic heat diffusion model taking into account the application dependent power load for thermal analysis. Then, we design the floorplanning algorithm based on this model. Experimental results show that, compared with the deterministic heat diffusion model, our model obtains up to...
Dual Vt assignment and input vector control are two tightly coupled leakage reduction techniques. We study how to apply them effectively to a circuit to minimize the static leakage power. We argue that simply combining them in a serial fashion will not reach their full potential in leakage reduction. To show this, we propose a heuristic algorithm that integrates them into a single optimization loop...
Timing budgeting under process variations is an important step in a statistical optimization flow. We propose a novel formulation of the problem where budgets are statistical instead of deterministic as in existing works. This new formulation considers the changes of both the means and variances of delays, and thus can reduce the timing violation introduced by ignoring the changes of variances. We...
Reconfigurable hardware is becoming a prominent component in a large variety of SoC designs. Reconfigurability allows for efficient hardware acceleration and virtually unlimited adaptability. On the other hand, overheads associated with reconfiguration and interfaces with the software component need to be evaluated carefully during the exploration phase. The aim of this paper is to identify the best...
Many computing systems have adopted the dynamic voltage scaling (DVS) technique to reduce energy consumption by slowing down operation speed. However, The longer a job executes, the more energy in leakage current the processor consumes for the job. To reduce the power/energy consumption from the leakage current, a processor can enter the dormant mode. Existing research results for leakage-aware DVS...
This paper describes the FAST methodology that enables a single FPGA to accelerate the performance of cycle-accurate computer system simulators modeling modem, realistic SoCs, embedded systems and standard desktop/laptop/server computer systems. The methodology partitions a simulator into (i) a functional model that simulates the functionality of the computer system and (ii) a predictive model that...
Stepwise refinement is at the core of many approaches to synthesis and optimization of hardware and software systems. For instance, it can be used to build a synthesis approach for digital circuits from high level specifications. It can also be used for post-synthesis modification such as in engineering change orders (ECOs). Therefore, checking if a system, modeled as a set of concurrent processes,...
Variable hiding and predicate abstraction are two popular abstraction methods to obtain simplified models for model checking. Although both methods have been used successfully in practice, no attempt has been made to combine them in counterexample guided abstraction refinement (CEGAR). In this paper, we propose a hybrid abstraction method that allows both visible variables and predicates to take advantages...
Retiming and resynthesis are among the most important techniques for practical sequential circuit optimization. However, their applicability is much limited due to verification concerns. Overcoming the verification bottleneck is a supreme task. This paper studies both the theoretical and practical aspects of inductive verification on the equivalence between circuits under retiming and resynthesis...
Design decisions made during high-level synthesis usually have great impacts on the later design stages. In this paper, We present a general framework, which plans for the clock skew-scheduling in physical design stages during register binding in high-level synthesis. Our proposed technique pursues the optimality of the native objective functions of the register binding problem. At the same time,...
The well-known Pelgrom model (S. Ray and B. Song, 2006) has demonstrated that the variation between two devices on the same die due to random mismatch is inversely proportional to the square root of the device area: sigma ~ 1/sqrt(Area). Based on the Pelgrom model, analog devices are sized to be large enough to werage out random variations. Importantly, with CMOS scaling, variations due to random...
This paper proposes an approach to non-robust and functionally sensitizable path delay test generation through stuck-at test generation. In this approach, to generate two-pattern tests for path delay faults in a combinational circuit, checker circuitry is constructed which is composed of logic gates corresponding to the mandatory assignments for detecting the faults. This checker circuitry allows...
In this paper, we present the first work on the Steiner routing for 3D stacked ICs. In the 3D Steiner routing problem, the pins are located in multiple device layers, which makes it more general than its 2D counterpart. Our algorithm consists of two steps: tree construction and tree refinement. Our tree construction algorithm builds a delay-oriented Steiner tree under a given thermal profile. We show...
This paper presents fully parallel domain decomposition (DO) techniques for efficient simulation of large-scale linear circuits such as power grids. DD techniques that use non-overlapping and overlapping partitioning of power grids are described in this paper. Simulation results show that with the proposed parallel DD framework, existing linear circuit simulators can be extended to handle large-scale...
Due to the recent advances in microfluids, digital microfluidic biochips are expected to revolutionize laboratory procedures. One critical problem for biochip synthesis is the droplet routing problem. Unlike traditional VLSI routing problems, in addition to routing path selection, the biochip routing problem needs to address the issue of scheduling droplets under the practical constraints imposed...
Electromigration (EM) and self-heating are critical reliability concerns for metal wires in high performance designs. EM reliability rules for a VLSI technology are typically expressed in terms of average, root-mean-square and peak current limits for each metal layer in the technology. To ensure EM reliability of a design, current flowing through each wire segment in the design should not violate...
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