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This paper addresses estimation of decoupling capacitance (decap) at sub-module stage based on their power dissipation and proper allocation of decap at the pre-layout level. Decap being in between power and ground distribution networks acts as local charge storage and effectively reduces rapid transients in the supply drop. Therefore, present trends in VLSI design are inclined towards the placement...
With the entry into the embedded domain, security of SOC architectures has become an arena of importance. However, complexity and cost factors have forced us to outsource the VLSI design phases across the globe. Such sites may not be trusted and threat lies in the introduction of malicious intrusions at any stage of the design flow. Such malicious intrusions, also known as Hardware Trojan Horses (HTH)...
With the progress in VLSI technology increase in circuit density is obvious. In present integrated circuits, electrical power is distributed to the large number of components of the chip over a network of on chip conductors. The systematic arrangement of the power distribution network (PDN) is commonly termed as power grid. The challenge of efficient PDN design escalates to a greater extent especially...
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