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A 12b 70MS/s sub-2 radix SAR ADC designed on Intel's 14nm tri-gate CMOS process is presented. It utilizes a startup calibration for correcting capacitor mismatches in its CDAC. The calibration is fully digital and doesn't require accurate references or input signals. The sub-2 radix architecture provides redundancy that improves speed. The comparator has a novel preamplifier that helps achieve low-noise...
A 4.06–4.89 GHz, low phase noise symmetric complementary voltage controlled oscillator (VCO), which features an optimized capacitive feedback technique combined with RC source degeneration, is presented in this paper. Fabricated in 180nm CMOS technology, the proposed VCO obtained a measured corner frequency of 15–80 KHz. The measured phase noise at 1MHz offset from the 4.89GHz carrier is −119dBc/Hz...
In a digital circuit system, IR drop effect can be alleviated by reducing the peak current of the system. Clock skew scheduling is a popular technique for peak current reduction. In this paper, we propose two algorithms that apply a Multiple Threshold CMOS (MTCMOS) technique rather than clock skew scheduling to do peak current reduction. MTCMOS techniques are feasible to reduce peak current because...
A microelectronic system capable of recording from and stimulating spinal nerves at injury intervals after surgical implantation has been designed. As require of implantable engineering for the regeneration microelectronic system, the system is low noise, low power, small size and high performance. Such system, will be implanted in body for recording from and stimulating the spinal nerve and contribute...
In this paper, we propose novel transmission-gate-based (TG-based) AND gates, TG-based OR gates, and pass-transistor logic gates that have new structures and have lower transistor counts than those proposed by other authors. All our proposed gates operate in full swing and have less leakage currents, less dynamic power consumption, and shorter delays than conventional CMOS gates. Compared with the...
We are searching for a way to generate neural function recovery by introducing an implantable microelectronic system. Prototypes of the so-called microelectronic neural-bridging systems have been realized in the form of integrated circuits. The integrated circuits were realized in a standard CMOS process. In a series of animal experiments, we have demonstrated that an interrupted spinal cord could...
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