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We have developed a fully logic-MOS-transistor designed on-chip digitally controlled LDO in 40 nm CMOS. The proposed TDC-based voltage sensor used as an ADC can reduce the offset error almost to zero. The area of this LDO with no analog circuits is only 0.057 mm2. To suppress the AC voltage drop due to large load transient (LLT), we developed a LLT control method using dynamic sampling clock frequency...
We propose a dynamic voltage-drop sensor, which is fully digital so that it is easy to design into products and use for testing. The 2.4K-gate GHz sensor exploits the difference in the voltage sensitivity between two paths composed of different types of standard cells. We have fabricated a test chip in a 28-nm HKMG process and confirmed its feasibility. This sensor can be used to evaluate optimal...
A fast transient-response digital low-dropout (LDO) voltage regulator comprising only low-voltage MOS transistors was developed. The input voltage can be higher than the withstand voltage of the low-voltage MOS transistors by the proposed withstand-voltage relaxation scheme. The switching frequency of 1 GHz can be achieved using small-dimension low-voltage power-MOS transistors. The LDO occupies only...
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