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In this paper, a novel triple reduced surface field (RESURF) LDMOS with N-top layer based on substrate termination technology (STT) is proposed. The analytical models of surface potential, surface electric field, breakdown voltage (BV) and optimal integrated charge of N-top layer (Qntop) for the novel triple RESURF LDMOS are achieved. Furthermore, STT is applied to avoid the premature avalanche breakdown...
NBTI of BOX layer induced degradation for thin layer SOI field p-channel LDMOS is investigated by experiment, modeling and simulation. Decrease in drain current (Id) under high negative BG voltage (VBG) stressing is observed, which is ascribed to the positive fixed oxide charge and interface charge in BOX layer induced by NBTI. The NBTI conduction modulation model is proposed to elevate the positive...
An ultra-low Ron, sp SOI LDMOS with an improved BV is proposed and its breakdown mechanism is investigated. The device features a variable-k dielectric trench and a P-pillar beside the trench (VK-P). The P-pillar extending from the P-body to the trench bottom not only acts as the vertical junction termination extension (JTE), but also forms an enhanced vertical RESURF (reduced surface field) structure...
Temperature-dependent ON-state breakdown (BVON) loci of AlGaN/GaN high-electron-mobility transistors (HEMTs) were experimentally demonstrated for the first time. With gate-current extraction technique, impact ionization was revealed to be responsible for the ON-state breakdown in our device as the HEMTs is marginally turned on. The characteristic electric-field Ei of impact ionization was extracted...
An improved breakdown voltage LDMOS with reduced specific on-resistance is proposed and its mechanism is investigated. The LDMOS is characterized by a junction-type field plate (JFP) and an N+ floating layer (NFL) in the p-substrate. First, the linear doped JFP not only modulates the surface electric field (E-field) distribution of the drift region to make it more uniform and thus increases the breakdown...
A novel n-channel VDMOS fabricated on 4H-SiC is reported. This device is a distinct double-layer structure with an ultra-thin n-doped region under a fully depleted p-body region in the channel region which induces a larger amount of carriers when the gate bias exceeds the threshold voltage, with little leakage current in off-state. As a result, the specific on-resistance of the VDMOS is 6.21 mΩ·cm...
A novel partial silicon-on-insulator (PSOI) high-voltage LDMOS is proposed and its breakdown mechanism is investigated numerically and experimentally. The PSOI LDMOS features double-sided charge trenches on the top and bottom interfaces of the buried oxide (BOX) (DTPSOI). In high-voltage blocking state, the charges located in the trenches enhance the electric field strength in the BOX, and a Si window...
A novel substrate-assisted (SA) RESURF technology aiming at improving off-state breakdown voltage (BV) of PN junction with small curvature radius is proposed and experimentally demonstrated in this paper. The SA RESURF technology not only realizes small curvature radius in the fingertip region, but also reduces electric field concentration in the curved metallurgical junction. Low-doped P-substrate,...
A superjunction LDMOST with a floating oppositely doped buried layer in p-substrate is proposed. The buried layer provides another pn junction to sustain drain voltage, reduces the substrate-assisted-depletion effect and generates new electric field, which modulates the bulk electric field in off-state. Simulation results show that the proposed structure achieves significant breakdown voltage improvement...
A lateral power MOSFET with the extended trench gate is proposed in this letter. The polysilicon gate electrode is extended to the substrate, which improves the breakdown voltage (BV) and specific on-resistance (Ron). It indicates by simulation that the Ron of 1.86mΩ.cm2 with a BV of 174V in the proposed structure is nearly 53% less than the Ron of 3.96mΩ.cm2 with a BV of 126V in the typical structure.
A new Membrane PSOI High Voltage Device with a Buried P+ layer (MBP+ PSOI) is proposed. Breakdown voltage is only decided by lateral breakdown voltage because of the entire removing of silicon substrate under the drift region and breakdown voltage can be improved with increase of the length of the drift region. Introducing of P+ layer can effectively reduce specific on-resistance and silicon window...
A high voltage LDMOS on partial silicon-on-insulator (PSOI) with a variable low-k (relative permittivity) dielectric buried layer (VLKD) and a buried p-layer (BP) is proposed (VLKD BPSOI). In the vertical direction, the low k value enhances the electric field strength in the buried dielectric (EI) and the Si window makes the substrate share the voltage drop, which leads to a high vertical breakdown...
This paper reports a novel Super Junction pLDMOS (SJ-pLDMOS) with charge-balanced SJ region at the surface of Variation Lateral Doping (VLD) drift region. SJ region provides a low on-resistance path in the ON-state and keeps charge balance approximately when the doping concentration of p pillars is slightly higher than that of the n pillars during the OFF-state. A significant reduction of the specific...
A novel non-uniform multi-reversed-junction power MOSFET is presented in this paper. The high and uniform electric field in substrate is achieved due to modulating from space charges in the buried layers during operation in the blocking mode, and the breakdown voltage is improved considerably. A detailed study of the influence of various important parameters on blocking characteristics was carried...
We propose a high voltage silicon-on-insulator (SOI) LDMOS with a Buried N-layer (BN SOI) in a self-isolation SOI high-voltage integrated circuit (HVIC). The ionized donors present in the BN enhance the interface silicon field strength from 10 V/μm of the conventional P-SOI (CP SOI) to 30 V/μm. As a result the maximum electric field in the buried oxide before the adjacent SOI breaks down (named E¡)...
This paper presents a high voltage AlGaN/GaN HEMTs with remarkable breakdown voltage enhancement by introducing a magnesium doping layer under the 2-DEG channel. The surface electric field is distributed more evenly when compare to a conventional device structure with the same dimensions. This is primarily due to the presence of a charge balanced magnesium doping layer acting as a floating field plate...
Based on ENDIF (ENhanced DIelectric layer Field), a new E-SIMOX high voltage device structure with the charge islands on the SOI and its breakdown mechanism proposed in this paper. The structure is characterized by the charge islands inserted on the top interface of silicon layer and dielectric layer. Inversion holes located by Coulomb's force enhance the electric field of the dielectric layer (EI...
A back-gate silicon on insulator (SOI) high voltage device with a compound layer (BG CL SOI-LDMOS) is proposed to enhance breakdown voltage of SOI device. Introducing of compound layer(CL) can effectively suppress gain of surface electric field at source side, and increase electric field in the buried oxide layer. Thus breakdown voltage of device is increased remarkably with invariable specific on-resistance...
Device simulations are applied to find out the effects of floating island thickness (dF) and doping concentration (Np+) in power floating island MOSFET (FLIMOS). The simulation results show that the specific on-resistance (Ronmiddotsp) increases by enlarging dF while Np+ produce little influence on Ronmiddotsp; When Np+ is low, the breakdown voltage (Vbr) improves by enlarging dF; When Np+ is high,...
A novel SOI high voltage device with a ring drain is developed. Junction curvature is introduced to enhance the breakdown voltage. As an example, Breakdown voltage over 600 V is achieved in a SOI LDMOS on the SOI material with 3 mum buried oxide and 20 mum silicon. Compared with normal structure, the breakdown voltage is increased by 6.74% and the on resistance is increased merely by 2.14%.The ring...
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