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A fully integrated 40-Gb/s transmitter and receiver chipset with SFI-5 interface was implemented in a 65-nm CMOS technology and mounted in a plastic BGA package. The transmitter chip provides a good jitter performance with a 40-GHz full-rate clock architecture that alleviates pattern-dependent jitter. The measured RMS jitter on the output was 570 to 900 fs at 39.8 Gb/s to 44.6 Gb/s using a 2^31-1...
This paper presents a fractional-sampling-rate (FSR) CDR that blindly samples the received signal with an ADC at 1.45x the data rate and estimates the data phase using a feedforward architecture for clock and data recovery. The presented architecture reduces the ADC power by 27.3% compared to a 2x CDR. Measurements confirm that the FSR CDR recovers data with BER<1013 at 6.875 Gb/s from samples...
An SSC-compliant 5 Gb/s transceiver in 65 nm CMOS is developed and tested. The receiver uses an ADC-based front-end that samples the incoming signal without adjusting the phase difference between the sampling clock and the signal. The phase tracking of the input signal and the data decision are performed entirely in the numerical domain.
A fully integrated 40 Gb/s transmitter and receiver chipset with SFI-5 interface is implemented in a 65 nm CMOS technology and mounted in a plastic BGA package. The transmitter chip provides good jitter performance with a 40 GHz full-rate clock architecture that alleviates pattern-dependent jitter and eliminates duty cycle dependence. The measured RMS jitter on the output is 570 fs to 900 fs over...
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