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A fully integrated 40-Gb/s transmitter and receiver chipset with SFI-5 interface was implemented in a 65-nm CMOS technology and mounted in a plastic BGA package. The transmitter chip provides a good jitter performance with a 40-GHz full-rate clock architecture that alleviates pattern-dependent jitter. The measured RMS jitter on the output was 570 to 900 fs at 39.8 Gb/s to 44.6 Gb/s using a 2^31-1...
Quadrature injection-lockedLC dividers with either a Miller topology or an injection-lockedLC VCO topology are coupled with transconductors to enhance their locking range. The effect of the transconductance coupling is analyzed theoretically and through circuit simulation. Both topologies were fabricated by 90-nm CMOS technology with a target input center frequency of 20 GHz and output frequency of...
We present the state-of-the-art 45nm high performance bulk logic platform technology which utilizes, for the first time in the industry, ultra high NA (1.07) immersion lithography to realize highly down-scaled chip size. Fully renovated MOSFET integration scheme which features reversed extension and SD diffusion formation is established to meet Vt roll-off requirement with excellent transistor performance...
A 20-GHz injection-locked LC divider is described. A Miller divider topology was employed along with a coupling circuit to maximize the locking range. A test chip designed in a 90nm CMOS technology operates at 20 GHz with 25% locking range while consuming 6.4 mW of power
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