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We demonstrated monolithic integration of pseudo-spin-MOSFETs (PS-MOSFETs) using vendor-made MOSFETs fabricated in a low-cost multi-project wafer (MPW) product and lab-made magnetic tunnel junctions (MTJs) formed on the topmost passivation film of the MPW chip. The tunneling magnetoresistance (TMR) ratio of the fabricated MTJs strongly depended on the surface roughness of the passivation film. Nevertheless,...
For 20nm SoC products, we propose an SRAM macro with low dynamic and leakage power. This is achieved by adopting an interleave word-line and hierarchical bit-line scheme, in which minimum portions of circuits are activated when SRAM is accessed. Measured data confirms that the proposed 128kb SRAM realizes 600 mV operation, 2.1 µW/MHz active power and 82 % leakage power reduction.
Summary form only given. Recently-proposed spin metal-oxide-semiconductor field-effect transistors (spin MOSFETs) are expected to be key devices for advancing the integrated circuit technology beyond the CMOS scaling. Towards the integration of spin MOSFETs with a CMOS platform, experimental demonstration and critical understanding of output characteristics are strongly needed. In this paper, we present...
The formation of ultra-shallow junction (USJ) less than 10 nm by using diffusion-less high-activation millisecond annealing technique has been investigated for deeply scaled planar bulk CMOS. This achievement relies on cross-sectional visualization of impurity distributions in MOSFET based on the electron beam holography technology with extremely high spatial resolution. Incorporation of cluster-ion...
Semiconductor-based spin transistors are expected to give a new spin degree of freedom in future electronics. While many different spin transistors have been proposed and studied, the spin MOSFET is one of the most promising devices, because it can have spin-dependent output characteristics, transistor functions, and good compatibility with existing silicon technology. The device concept, structures...
Sub-30nm MOSFET fabrication technology is proposed based on a dedicated process redesign suitable for a non-melt laser annealing technique. Two major features of the laser annealing (LA), i.e. diffusion-less and higher dopant activation enable us to apply more elaborate channel engineering, involving multiple halo implantations and optimized gate-predoping, that contributes further scaling of a functional...
We found a new anomalous gate leakage current (AGLC) of ultra-thin gate-SiON, which may directly impact standby leakage and yield for 65 nm node and beyond. We have identified the AGLC mechanism and also developed gate-stack fabrication process as effective countermeasures. Reducing gate-SiON to less than 1.3 nm induces AGLC leading to reliability degradation in nFET. With relatively large Phosphorous...
An elevated central-channel doping with a depth similar to the S/D junctions is proposed as the best measure for simultaneously improving MOSFET device and high speed circuit performances as well as minimizing their fluctuations. We base our arguments on hydrodynamic device simulation, measured device data of vertical MOSFETs with a central delta-doped impurity profile and include experimental results...
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