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A multi-step word-line control technology (MWC), combined with a new hierarchical cell SRAM architecture (HCA), has been developed to overcome rapid increase in random variability with no area penalty. A 40-nm-node 0.248-μm2-cell SRAM using a single power supply has been successfully fabricated, pushing up bit density to 2.98 Mb/mm2. MWC improved VDD_min@-6σ by 0.34 V and 0.22 V for read and write...
A new hierarchical cell SRAM architecture, combined with a multi-step word-line control technology, has been developed to overcome rapid increase in random variability with no area-penalty. A 40nm-node 0.248 μm2-cell SRAM using a single power supply has been successfully fabricated, pushing up bit-density to 2.98Mb/mm2.
A new accelerated testing scheme for detecting SRAM bit failure caused by random telegraph noise (RTN) is proposed. By repeatedly monitoring the fail bit count (FBC) under a reduced margin operation condition, increasing trend of FBC along time was clearly observed, which is believed to be caused by RTN. In addition, physics-based ultra-fast Monte Carlo RTN simulation program has been developed, which...
For the first time, we demonstrate standard cell gate density of 3650 KGate/mm2 and SRAM cell of 0.124 mum2 for 32 nm CMOS platform technology. Both advanced single exposure (SE) lithography and gate-first metal gate/high-k (MG/HK) process contribute to reduce total cost per function by 50% from 45 nm technology node, which is unattainable by dual exposure (DE) lithography or double patterning (DP)...
Enhancement mechanism of Vth fluctuation in saturation region is analyzed through addressable transistor array measurement and 3D Monte-Carlo TCAD simulation. It was confirmed that random dopant fluctuation (RDF) in heavily doped halo devices enhances source-drain asymmetry, resulting in non-Gaussian distributions of DIBL and saturation Vth (Vth_sat). The measured DIBL behavior was accurately modeled...
We redefine write margin in order to be able to quantify the effect of both PVT variation and write-margin improvement. A write-margin monitoring circuit based on this definition is implemented in a 90nm CMOS process. This circuit can be applied to an SRAM power supply circuit to improve the write margin
A read-static-noise-margin-free SRAM cell consists of seven transistors, several of which are low-V, NMOS transistors used to achieve both low-V/sub dd/ and high-speed operation. A 64 kb SRAM macro is fabricated in 90 nm CMOS technology. Both a minimum V/sub dd/ of 440 mV and a 20 ns access time with a 0.5 V supply are obtained.
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